component
STM8S207S8T3C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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STM8S207S8T3C
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STM8S207S8T3C from STMicroelectronics, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin (I/O type, main function Reset); its electrical limits are in Section 10.3.7, which is not in this excerpt. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O, with alternate function resonator/crystal oscillator input (OSCIN), slow output speed O1 (up to 2 MHz). |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O, with alternate function resonator/crystal oscillator output (OSCOUT), slow output speed O1 (up to 2 MHz). |
| 4 | VSSIO_1 | power_in | I/O ground pin for the I/O ring. |
| 5 | VSS | power_in | Digital ground pin. |
| 6 | VCAP | passive | 1.8 V regulator capacitor pin, which requires an external capacitor (see Section 10.3.1). |
| 7 | VDD | power_in | Digital power supply pin (operating range 2.95 V to 5.5 V per the features list). |
| 8 | VDDIO_1 | power_in | I/O power supply pin. |
| 9 | PA4/UART1_RX | bidirectional | Port A4 I/O with UART1 receive function, high sink capable (HS) and fast/slow programmable output (O3); its default state is controlled by the ROM bootloader, which pulls it up during bootloader activation and returns it to floating before the bootloader exits. |
| 10 | PA5/UART1_TX | bidirectional | Port A5 I/O with UART1 transmit function, high sink capable (HS) and fast/slow programmable output (O3). |
| 11 | PA6/UART1_CK | bidirectional | Port A6 I/O with UART1 synchronous clock function, high sink capable (HS) and fast/slow programmable output (O3). |
| 12 | VDDA | power_in | Analog power supply pin for the ADC. |
| 13 | VSSA | power_in | Analog ground pin. |
| 14 | PB7/AIN7 | bidirectional | Port B7 I/O with analog input 7 (AIN7), slow output speed O1. |
| 15 | PB6/AIN6 | bidirectional | Port B6 I/O with analog input 6 (AIN6), slow output speed O1. |
| 16 | PB5/AIN5 | bidirectional | Port B5 I/O with analog input 5 (AIN5); I2C_SDA is available as an alternate function after remap (AFR6). |
| 17 | PB4/AIN4 | bidirectional | Port B4 I/O with analog input 4 (AIN4); I2C_SCL is available as an alternate function after remap (AFR6). |
| 18 | PB3/AIN3 | bidirectional | Port B3 I/O with analog input 3 (AIN3); TIM1_ETR is available as an alternate function after remap (AFR5). |
| 19 | PB2/AIN2 | bidirectional | Port B2 I/O with analog input 2 (AIN2); TIM1_CH3N is available as an alternate function after remap (AFR5). |
| 20 | PB1/AIN1 | bidirectional | Port B1 I/O with analog input 1 (AIN1); TIM1_CH2N is available as an alternate function after remap (AFR5). |
| 21 | PB0/AIN0 | bidirectional | Port B0 I/O with analog input 0 (AIN0); TIM1_CH1N is available as an alternate function after remap (AFR5). |
| 22 | PE6/AIN9 | bidirectional | Port E6 I/O with analog input 9 (AIN9), slow output speed O1. |
| 23 | PE5/SPI_NSS | bidirectional | Port E5 I/O with SPI master/slave select function (SPI_NSS), slow output speed O1. |
| 24 | PC1/TIM1_CH1 | bidirectional | Port C1 I/O with Timer 1 channel 1 function, high sink capable (HS) and fast/slow programmable output (O3). |
| 25 | PC2/TIM1_CH2 | bidirectional | Port C2 I/O with Timer 1 channel 2 function, high sink capable (HS) and fast/slow programmable output (O3). |
| 26 | PC3/TIM1_CH3 | bidirectional | Port C3 I/O with Timer 1 channel 3 function, high sink capable (HS) and fast/slow programmable output (O3). |
| 27 | PC5/SPI_SCK | bidirectional | Port C5 I/O with SPI clock function (SPI_SCK), high sink capable (HS) and fast/slow programmable output (O3). |
| 28 | VSSIO_2 | power_in | I/O ground pin for the I/O ring. |
| 29 | VDDIO_2 | power_in | I/O power supply pin. |
| 30 | PC6/SPI_MOSI | bidirectional | Port C6 I/O with SPI master out / slave in function (SPI_MOSI), high sink capable (HS) and fast/slow programmable output (O3). |
| 31 | PC7/SPI_MISO | bidirectional | Port C7 I/O with SPI master in / slave out function (SPI_MISO), high sink capable (HS) and fast/slow programmable output (O3). |
| 32 | PG0/CAN_TX | bidirectional | Port G0 I/O with beCAN transmit function (CAN_TX) listed in the pin table, but the datasheet states the beCAN interface is available on STM8S208xx devices only. |
| 33 | PG1/CAN_RX | bidirectional | Port G1 I/O with beCAN receive function (CAN_RX) listed in the pin table, but the datasheet states the beCAN interface is available on STM8S208xx devices only. |
| 34 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain I/O (T: P-buffer, weak pull-up and protection diode to VDD not implemented) carrying the I2C data line (I2C_SDA). |
| 35 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain I/O (T: P-buffer, weak pull-up and protection diode to VDD not implemented) carrying the I2C clock line (I2C_SCL). |
| 36 | PE0/CLK_CCO | bidirectional | Port E0 I/O with configurable clock output function (CLK_CCO), high sink capable (HS) and fast/slow programmable output (O3). |
| 37 | PD0/TIM3_CH2 | bidirectional | Port D0 I/O with Timer 3 channel 2 function, high sink capable (HS); TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are alternate functions after remap. |
| 38 | PD1/SWIM | bidirectional | Port D1 I/O with SWIM data interface function, high sink capable (HS); it is in input pull-up during the reset phase and after internal reset release. |
| 39 | PD2/TIM3_CH1 | bidirectional | Port D2 I/O with Timer 3 channel 1 function, high sink capable (HS); TIM2_CH3 (AFR1) is an alternate function after remap. |
| 40 | PD3/TIM2_CH2 | bidirectional | Port D3 I/O with Timer 2 channel 2 function, high sink capable (HS); ADC_ETR (AFR0) is an alternate function after remap. |
| 41 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 I/O with Timer 2 channel 1 function, high sink capable (HS); BEEP output (AFR7) is an alternate function after remap. |
| 42 | PD5/UART3_TX | bidirectional | Port D5 I/O with UART3 data transmit function, slow output speed O1. |
| 43 | PD6/UART3_RX | bidirectional | Port D6 I/O with UART3 data receive function, slow output speed O1; its default state is controlled by the ROM bootloader, which pulls it up during bootloader activation and returns it to floating before the bootloader exits. |
| 44 | PD7/TLI | bidirectional | Port D7 I/O with top level interrupt function (TLI), slow output speed O1; TIM1_CH4 (AFR4) is an alternate function after remap and is available on the 44-pin package only. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
CAD (KiCad official)
- Symbol:
STM8S207S8T3C - Footprint:
Package_QFP:LQFP-44_10x10mm_P0.8mm - 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm8s207s8t3c-etched.step/stm8s207s8t3c-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s207s8t3c.step/stm8s207s8t3c.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (117 pp, sha256
7adeaa849cf9e22f, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM8S207S8T3C
**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STM8S207S8T3C from STMicroelectronics, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin (I/O type, main function Reset); its electrical limits are in Section 10.3.7, which is not in this excerpt. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O, with alternate function resonator/crystal oscillator input (OSCIN), slow output speed O1 (up to 2 MHz). |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O, with alternate function resonator/crystal oscillator output (OSCOUT), slow output speed O1 (up to 2 MHz). |
| 4 | VSSIO_1 | power_in | I/O ground pin for the I/O ring. |
| 5 | VSS | power_in | Digital ground pin. |
| 6 | VCAP | passive | 1.8 V regulator capacitor pin, which requires an external capacitor (see Section 10.3.1). |
| 7 | VDD | power_in | Digital power supply pin (operating range 2.95 V to 5.5 V per the features list). |
| 8 | VDDIO_1 | power_in | I/O power supply pin. |
| 9 | PA4/UART1_RX | bidirectional | Port A4 I/O with UART1 receive function, high sink capable (HS) and fast/slow programmable output (O3); its default state is controlled by the ROM bootloader, which pulls it up during bootloader activation and returns it to floating before the bootloader exits. |
| 10 | PA5/UART1_TX | bidirectional | Port A5 I/O with UART1 transmit function, high sink capable (HS) and fast/slow programmable output (O3). |
| 11 | PA6/UART1_CK | bidirectional | Port A6 I/O with UART1 synchronous clock function, high sink capable (HS) and fast/slow programmable output (O3). |
| 12 | VDDA | power_in | Analog power supply pin for the ADC. |
| 13 | VSSA | power_in | Analog ground pin. |
| 14 | PB7/AIN7 | bidirectional | Port B7 I/O with analog input 7 (AIN7), slow output speed O1. |
| 15 | PB6/AIN6 | bidirectional | Port B6 I/O with analog input 6 (AIN6), slow output speed O1. |
| 16 | PB5/AIN5 | bidirectional | Port B5 I/O with analog input 5 (AIN5); I2C_SDA is available as an alternate function after remap (AFR6). |
| 17 | PB4/AIN4 | bidirectional | Port B4 I/O with analog input 4 (AIN4); I2C_SCL is available as an alternate function after remap (AFR6). |
| 18 | PB3/AIN3 | bidirectional | Port B3 I/O with analog input 3 (AIN3); TIM1_ETR is available as an alternate function after remap (AFR5). |
| 19 | PB2/AIN2 | bidirectional | Port B2 I/O with analog input 2 (AIN2); TIM1_CH3N is available as an alternate function after remap (AFR5). |
| 20 | PB1/AIN1 | bidirectional | Port B1 I/O with analog input 1 (AIN1); TIM1_CH2N is available as an alternate function after remap (AFR5). |
| 21 | PB0/AIN0 | bidirectional | Port B0 I/O with analog input 0 (AIN0); TIM1_CH1N is available as an alternate function after remap (AFR5). |
| 22 | PE6/AIN9 | bidirectional | Port E6 I/O with analog input 9 (AIN9), slow output speed O1. |
| 23 | PE5/SPI_NSS | bidirectional | Port E5 I/O with SPI master/slave select function (SPI_NSS), slow output speed O1. |
| 24 | PC1/TIM1_CH1 | bidirectional | Port C1 I/O with Timer 1 channel 1 function, high sink capable (HS) and fast/slow programmable output (O3). |
| 25 | PC2/TIM1_CH2 | bidirectional | Port C2 I/O with Timer 1 channel 2 function, high sink capable (HS) and fast/slow programmable output (O3). |
| 26 | PC3/TIM1_CH3 | bidirectional | Port C3 I/O with Timer 1 channel 3 function, high sink capable (HS) and fast/slow programmable output (O3). |
| 27 | PC5/SPI_SCK | bidirectional | Port C5 I/O with SPI clock function (SPI_SCK), high sink capable (HS) and fast/slow programmable output (O3). |
| 28 | VSSIO_2 | power_in | I/O ground pin for the I/O ring. |
| 29 | VDDIO_2 | power_in | I/O power supply pin. |
| 30 | PC6/SPI_MOSI | bidirectional | Port C6 I/O with SPI master out / slave in function (SPI_MOSI), high sink capable (HS) and fast/slow programmable output (O3). |
| 31 | PC7/SPI_MISO | bidirectional | Port C7 I/O with SPI master in / slave out function (SPI_MISO), high sink capable (HS) and fast/slow programmable output (O3). |
| 32 | PG0/CAN_TX | bidirectional | Port G0 I/O with beCAN transmit function (CAN_TX) listed in the pin table, but the datasheet states the beCAN interface is available on STM8S208xx devices only. |
| 33 | PG1/CAN_RX | bidirectional | Port G1 I/O with beCAN receive function (CAN_RX) listed in the pin table, but the datasheet states the beCAN interface is available on STM8S208xx devices only. |
| 34 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain I/O (T: P-buffer, weak pull-up and protection diode to VDD not implemented) carrying the I2C data line (I2C_SDA). |
| 35 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain I/O (T: P-buffer, weak pull-up and protection diode to VDD not implemented) carrying the I2C clock line (I2C_SCL). |
| 36 | PE0/CLK_CCO | bidirectional | Port E0 I/O with configurable clock output function (CLK_CCO), high sink capable (HS) and fast/slow programmable output (O3). |
| 37 | PD0/TIM3_CH2 | bidirectional | Port D0 I/O with Timer 3 channel 2 function, high sink capable (HS); TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are alternate functions after remap. |
| 38 | PD1/SWIM | bidirectional | Port D1 I/O with SWIM data interface function, high sink capable (HS); it is in input pull-up during the reset phase and after internal reset release. |
| 39 | PD2/TIM3_CH1 | bidirectional | Port D2 I/O with Timer 3 channel 1 function, high sink capable (HS); TIM2_CH3 (AFR1) is an alternate function after remap. |
| 40 | PD3/TIM2_CH2 | bidirectional | Port D3 I/O with Timer 2 channel 2 function, high sink capable (HS); ADC_ETR (AFR0) is an alternate function after remap. |
| 41 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 I/O with Timer 2 channel 1 function, high sink capable (HS); BEEP output (AFR7) is an alternate function after remap. |
| 42 | PD5/UART3_TX | bidirectional | Port D5 I/O with UART3 data transmit function, slow output speed O1. |
| 43 | PD6/UART3_RX | bidirectional | Port D6 I/O with UART3 data receive function, slow output speed O1; its default state is controlled by the ROM bootloader, which pulls it up during bootloader activation and returns it to floating before the bootloader exits. |
| 44 | PD7/TLI | bidirectional | Port D7 I/O with top level interrupt function (TLI), slow output speed O1; TIM1_CH4 (AFR4) is an alternate function after remap and is available on the 44-pin package only. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
## CAD (KiCad official)
- Symbol: `STM8S207S8T3C`
- Footprint: `Package_QFP:LQFP-44_10x10mm_P0.8mm`
- 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm8s207s8t3c-etched.step` / `stm8s207s8t3c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s207s8t3c.step` / `stm8s207s8t3c.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922319138140160) (117 pp, sha256 `7adeaa849cf9e22f`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm8s207s8t3c-datasheet.pdf)