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STM8S207RBT6TR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm8s207rbt6trfactory-2.0.0extractor-text

Verified STM8S207RBT6TR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: STM8S207RBT6TR · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 117-page datasheet
  • ✓distributor: lcsc C2971533, digikey 497-19685-2-ND, mouser 511-STM8S207RBT6TR
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-48aesyc3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ stm8s207rbt6tr.kicad_sym✓ stm8s207rbt6tr.kicad_mod✓ stm8s207rbt6tr.step
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Ray Publish 0.1.0 0246c8e 8h ago

STM8S207RBT6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM8S207RBT6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Reset pin (NRST) whose reset pull-up and timing limits are given in section 10.3.7 of the datasheet.
2 PA1/OSCIN bidirectional Port A1 with resonator or crystal oscillator input (OSCIN) and slow output speed O1 (up to 2 MHz).
3 PA2/OSCOUT bidirectional Port A2 with resonator or crystal oscillator output (OSCOUT) and slow output speed O1 (up to 2 MHz).
4 VSSIO_1 power_in I/O ground for the first I/O bank.
5 VSS power_in Digital ground.
6 VCAP passive Connection for the 1.8 V regulator external capacitor.
7 VDD power_in Digital power supply.
8 VDDIO_1 power_in I/O power supply for the first I/O bank.
9 PA3/TIM2_CH3 bidirectional Port A3 general I/O with Timer 2 channel 3 as default alternate function and TIM3_CH1 available after remap (AFR1).
10 PA4/UART1_RX bidirectional Port A4 high sink I/O (HS) with UART1 receive function, whose default state is controlled by the ROM bootloader.
11 PA5/UART1_TX bidirectional Port A5 high sink I/O (HS) with UART1 transmit function.
12 PA6/UART1_CK bidirectional Port A6 high sink I/O (HS) with UART1 synchronous clock function.
13 PF7/AIN15 bidirectional Port F7 I/O with ADC analog input 15.
14 PF6/AIN14 bidirectional Port F6 I/O with ADC analog input 14.
15 PF5/AIN13 bidirectional Port F5 I/O with ADC analog input 13.
16 PF4/AIN12 bidirectional Port F4 I/O with ADC analog input 12.
17 PF3/AIN11 bidirectional Port F3 I/O with ADC analog input 11.
18 VREF+ power_in ADC positive reference voltage.
19 VDDA power_in Analog power supply.
20 VSSA power_in Analog ground.
21 VREF- power_in ADC negative reference voltage.
22 PF0/AIN10 bidirectional Port F0 I/O with ADC analog input 10.
23 PB7/AIN7 bidirectional Port B7 I/O with ADC analog input 7.
24 PB6/AIN6 bidirectional Port B6 I/O with ADC analog input 6.
25 PB5/AIN5 bidirectional Port B5 I/O with ADC analog input 5 and I2C_SDA available after remap (AFR6).
26 PB4/AIN4 bidirectional Port B4 I/O with ADC analog input 4 and I2C_SCL available after remap (AFR6).
27 PB3/AIN3 bidirectional Port B3 I/O with ADC analog input 3 and TIM1_ETR available after remap (AFR5).
28 PB2/AIN2 bidirectional Port B2 I/O with ADC analog input 2 and TIM1_CH3N available after remap (AFR5).
29 PB1/AIN1 bidirectional Port B1 I/O with ADC analog input 1 and TIM1_CH2N available after remap (AFR5).
30 PB0/AIN0 bidirectional Port B0 I/O with ADC analog input 0 and TIM1_CH1N available after remap (AFR5).
31 PE7/AIN8 bidirectional Port E7 I/O with ADC analog input 8.
32 PE6/AIN9 bidirectional Port E6 I/O with ADC analog input 9.
33 PE5/SPI_NSS bidirectional Port E5 I/O with SPI master or slave select function.
34 PC1/TIM1_CH1 bidirectional Port C1 high sink I/O (HS) with Timer 1 channel 1 function.
35 PC2/TIM1_CH2 bidirectional Port C2 high sink I/O (HS) with Timer 1 channel 2 function.
36 PC3/TIM1_CH3 bidirectional Port C3 high sink I/O (HS) with Timer 1 channel 3 function.
37 PC4/TIM1_CH4 bidirectional Port C4 high sink I/O (HS) with Timer 1 channel 4 function.
38 PC5/SPI_SCK bidirectional Port C5 high sink I/O (HS) with SPI clock function.
39 VSSIO_2 power_in I/O ground for the second I/O bank.
40 VDDIO_2 power_in I/O power supply for the second I/O bank.
41 PC6/SPI_MOSI bidirectional Port C6 high sink I/O (HS) with SPI master out or slave in function.
42 PC7/SPI_MISO bidirectional Port C7 high sink I/O (HS) with SPI master in or slave out function.
43 PG0/CAN_TX bidirectional Port G0 I/O with beCAN transmit function, which is available on STM8S208xx devices only.
44 PG1/CAN_RX bidirectional Port G1 I/O with beCAN receive function, which is available on STM8S208xx devices only.
45 PG2 bidirectional Port G2 general I/O with slow output speed O1 (up to 2 MHz).
46 PG3 bidirectional Port G3 general I/O with slow output speed O1 (up to 2 MHz).
47 PG4 bidirectional Port G4 general I/O with slow output speed O1 (up to 2 MHz).
48 PI0 bidirectional Port I0 general I/O with slow output speed O1 (up to 2 MHz).
49 PG5 bidirectional Port G5 general I/O with slow output speed O1 (up to 2 MHz).
50 PG6 bidirectional Port G6 general I/O with slow output speed O1 (up to 2 MHz).
51 PG7 bidirectional Port G7 general I/O with slow output speed O1 (up to 2 MHz).
52 PE4 bidirectional Port E4 general I/O with slow output speed O1 (up to 2 MHz).
53 PE3/TIM1_BKIN bidirectional Port E3 I/O with Timer 1 break input function.
54 PE2/I2C_SDA bidirectional Port E2 true open drain I/O (T) with I2C data function, whose P-buffer and protection diode to VDD are not implemented.
55 PE1/I2C_SCL bidirectional Port E1 true open drain I/O (T) with I2C clock function, whose P-buffer and protection diode to VDD are not implemented.
56 PE0/CLK_CCO bidirectional Port E0 high sink I/O (HS) with configurable clock output function (CLK_CCO).
57 PD0/TIM3_CH2 bidirectional Port D0 high sink I/O (HS) with Timer 3 channel 2 function, TIM1_BKIN available after remap (AFR3) and CLK_CCO after remap (AFR2).
58 PD1/SWIM bidirectional Port D1 high sink I/O (HS) with SWIM data interface function, which is in input pull-up during the reset phase.
59 PD2/TIM3_CH1 bidirectional Port D2 high sink I/O (HS) with Timer 3 channel 1 function and TIM2_CH3 available after remap (AFR1).
60 PD3/TIM2_CH2 bidirectional Port D3 high sink I/O (HS) with Timer 2 channel 2 function and ADC_ETR available after remap (AFR0).
61 PD4/TIM2_CH1/BEEP bidirectional Port D4 high sink I/O (HS) with Timer 2 channel 1 function and BEEP output available after remap (AFR7).
62 PD5/UART3_TX bidirectional Port D5 I/O with UART3 data transmit function.
63 PD6/UART3_RX bidirectional Port D6 I/O with UART3 data receive function, whose default state is controlled by the ROM bootloader.
64 PD7/TLI bidirectional Port D7 I/O with top level interrupt (TLI) function.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (including VDDA and VDDIO) VDDx - VSS -0.3 6.5 V 54
Variations between different power pins /VDDx - VDD/ 50 mV 54
Variations between all ground pins /VSSx - VSS/ 50 mV 54
Total current into VDD power lines (source) IVDD 60 mA 55
Total current out of VSS ground lines (sink) IVSS 60 mA 55
Output current sunk by any I/O and control pin IIO 20 mA 55
Output current sourced by any I/O and control pin IIO 20 mA 55
Total output current sourced, devices with two VDDIO pins IIO 200 mA 55
Total output current sourced, devices with one VDDIO pin IIO 100 mA 55
Total output current sunk, devices with two VSSIO pins IIO 160 mA 55
Total output current sunk, devices with one VSSIO pin IIO 80 mA 55
Injected current on NRST pin IINJ(PIN) -4 4 mA 55
Injected current on OSCIN pin IINJ(PIN) -4 4 mA 55
Injected current on any other pin IINJ(PIN) -4 4 mA 55
Total injected current (sum of all I/O and control pins) IINJ(PIN) -20 20 mA 55
Storage temperature range TSTG -65 150 °C 55
Maximum junction temperature TJ 150 °C 55
Internal CPU clock frequency fCPU 0 24 MHz TA ≤ 105 °C 56
Internal CPU clock frequency fCPU 0 16 MHz 56
Standard operating voltage VDD/VDD_IO 2.95 5.5 V 56
Capacitance of external capacitor CEXT 470 3300 nF 56
ESR of external capacitor ESR 0.3 Ω at 1 MHz 56
ESL of external capacitor ESL 15 nH 56
Power dissipation, 44/48/64/80-pin devices PD 443 mW TA = 85 °C for suffix 6; 8 standard, 2 high sink, 2 open drain ports simultaneously 56
Ambient temperature for 6 suffix version TA -40 85 °C Maximum power dissipation 56
Junction temperature range, 6 suffix version TJ -40 105 °C 56
VDD rise time rate tVDD 2 µs/V 57
VDD fall time rate tVDD 2 µs/V 57
Reset release delay, VDD rising tTEMP 1.7 ms 57
Power-on reset threshold VIT+ 2.65 2.8 2.95 V 57
Brown-out reset threshold VIT- 2.58 2.73 2.88 V 57
Total current consumption, run mode, code from RAM, HSE crystal osc. IDD(RUN) 7.3 mA VDD = 5 V; fCPU = fMASTER = 24 MHz, TA ≤ 105 °C; HSE user ext. clock (24 MHz) 58
Total current consumption, run mode, code from RAM IDD(RUN) 5.8 mA VDD = 5 V; fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) 58
Total current consumption, run mode, code from RAM IDD(RUN) 3.4 mA VDD = 5 V; fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) 58
Total current consumption, run mode, code from RAM IDD(RUN) 4.1 mA VDD = 5 V; fCPU = fMASTER/128 = 125 kHz; HSE user ext. clock (16 MHz) 58
Total current consumption, run mode, code from RAM IDD(RUN) 1.3 mA VDD = 5 V; fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz) 58
Total current consumption, run mode, code from Flash IDD(RUN) 18 mA VDD = 5 V; fCPU = fMASTER = 24 MHz, TA ≤ 105 °C; HSE user ext. clock (24 MHz) 58
Total current consumption, run mode, code from Flash IDD(RUN) 15.2 mA VDD = 5 V; fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) 58
Total current consumption, run mode, code from Flash IDD(RUN) 13.2 mA VDD = 5 V; fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) 58
Total current consumption in wait mode IDD(WFI) 4.7 mA VDD = 5 V; fCPU = fMASTER = 24 MHz, TA ≤ 105 °C; HSE user ext. clock (24 MHz) 60
Total current consumption in wait mode IDD(WFI) 4.4 mA VDD = 5 V; fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) 60
Total current consumption in wait mode IDD(WFI) 1.6 mA VDD = 5 V; fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) 60
Total current consumption in active halt mode, MVR on, Flash operating mode IDD(AH) 200 260 µA VDD = 5 V; TA -40 to 85 °C; LSI RC oscillator (128 kHz) 61
Total current consumption in active halt mode, MVR off, Flash power-down mode IDD(AH) 11 45 µA VDD = 5 V; TA -40 to 85 °C; LSI RC oscillator (128 kHz) 61
Total current consumption in halt mode, Flash power-down, HSI clock after wakeup IDD(H) 6.5 35 µA VDD = 5 V; max at 85 °C 62
Internal RC oscillator accuracy, trimmed by CLK_HSITRIMR ACCHSI -1 1 % Trimmed by the CLK_HSITRIMR register for given VDD and TA conditions 67
Accuracy of HSI oscillator, factory calibrated ACCHSI -1.5 1.5 % VDD = 5 V, TA = 25 °C 67
Accuracy of HSI oscillator, factory calibrated ACCHSI -2.2 2.2 % VDD ≤ 5 V, 25 °C ≤ TA ≤ 85 °C 67
Accuracy of HSI oscillator, factory calibrated ACCHSI -3 3 % 2.95 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C 67
HSI oscillator power consumption IDD(HSI) 170 250 µA 67
LSI oscillator frequency fLSI 110 128 146 kHz 68
Erase/write cycles (program memory) NRW 10 kcycles TA ≤ 85 °C 69
Data retention (program memory) after 10 k erase/write cycles tRET 20 years TRET = 55 °C; TA ≤ 85 °C 69
Erase/write cycles (data memory) NRW 300 kcycles TA = 125 °C 69
Pull-up resistor Rpu 30 55 80 kΩ VDD = 5 V, VIN = VSS 70
Output low level with 8 pins sunk VOL 2 V IIO = 10 mA, VDD = 5 V 72
Output high level with 8 pins sourced VOH 2.8 V IIO = 10 mA, VDD = 5 V 72
Thermal resistance junction-ambient, LQFP 64 - 10 x 10 mm θJA 46 °C/W JEDEC JESD51-2, 4-layer PCB, natural convection 108
VHYS hysteresis, brown-out reset VHYS(BOR) 70 mV 57

CAD (KiCad official)

  • Symbol: STM8S207RBT6TR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm8s207rbt6tr-etched.step / stm8s207rbt6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s207rbt6tr.step / stm8s207rbt6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 2e4ffc955a4a2e95, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF