# STM8S207RBT6CTR

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(14x14)

STM8S207RBT6CTR from STMicroelectronics, in a LQFP-64(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin, listed in Table 6 as an I/O with Reset as its main function; its electrical limits are in section 10.3.7, which is not in the supplied pages. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O whose default alternate function is the resonator/crystal input OSCIN, with slow output speed O1 (up to 2 MHz). |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O whose default alternate function is the resonator/crystal output OSCOUT, with slow output speed O1 (up to 2 MHz). |
| 4 | VSSIO_1 | power_in | I/O ground for the I/O ring. |
| 5 | VSS | power_in | Digital ground. |
| 6 | VCAP | power_in | 1.8 V regulator capacitor pin; the external VCAP capacitor requirements are given in section 10.3.1. |
| 7 | VDD | power_in | Digital power supply; the device operating voltage is stated as 2.95 to 5.5 V. |
| 8 | VDDIO_1 | power_in | I/O power supply. |
| 9 | PA3/TIM2_CH3 | bidirectional | Port A3 I/O with default alternate function Timer 2 channel 3 and TIM3_CH1 as the alternate function after remap [AFR1], slow output speed O1. |
| 10 | PA4/UART1_RX | bidirectional | Port A4 I/O with UART1 receive as default alternate function; high-sink capable (HS), and the ROM bootloader pulls this pin up during activation before returning it to floating. |
| 11 | PA5/UART1_TX | bidirectional | Port A5 I/O with UART1 transmit as default alternate function; high-sink capable (HS). |
| 12 | PA6/UART1_CK | bidirectional | Port A6 I/O with UART1 synchronous clock as default alternate function; high-sink capable (HS). |
| 13 | PF7/AIN15 | bidirectional | Port F7 I/O with ADC analog input AIN15, slow output speed O1. |
| 14 | PF6/AIN14 | bidirectional | Port F6 I/O with ADC analog input AIN14, slow output speed O1. |
| 15 | PF5/AIN13 | bidirectional | Port F5 I/O with ADC analog input AIN13, slow output speed O1. |
| 16 | PF4/AIN12 | bidirectional | Port F4 I/O with ADC analog input AIN12, slow output speed O1. |
| 17 | PF3/AIN11 | bidirectional | Port F3 I/O with ADC analog input AIN11, slow output speed O1. |
| 18 | VREF+ | power_in | ADC positive reference voltage. |
| 19 | VDDA | power_in | Analog power supply. |
| 20 | VSSA | power_in | Analog ground. |
| 21 | VREF- | power_in | ADC negative reference voltage. |
| 22 | PF0/AIN10 | bidirectional | Port F0 I/O with ADC analog input AIN10, slow output speed O1. |
| 23 | PB7/AIN7 | bidirectional | Port B7 I/O with ADC analog input AIN7, slow output speed O1. |
| 24 | PB6/AIN6 | bidirectional | Port B6 I/O with ADC analog input AIN6, slow output speed O1. |
| 25 | PB5/AIN5 | bidirectional | Port B5 I/O with ADC analog input AIN5; I2C_SDA is available as the alternate function after remap [AFR6]. |
| 26 | PB4/AIN4 | bidirectional | Port B4 I/O with ADC analog input AIN4; I2C_SCL is available as the alternate function after remap [AFR6]. |
| 27 | PB3/AIN3 | bidirectional | Port B3 I/O with ADC analog input AIN3; TIM1_ETR is available as the alternate function after remap [AFR5]. |
| 28 | PB2/AIN2 | bidirectional | Port B2 I/O with ADC analog input AIN2; TIM1_CH3N is available as the alternate function after remap [AFR5]. |
| 29 | PB1/AIN1 | bidirectional | Port B1 I/O with ADC analog input AIN1; TIM1_CH2N is available as the alternate function after remap [AFR5]. |
| 30 | PB0/AIN0 | bidirectional | Port B0 I/O with ADC analog input AIN0; TIM1_CH1N is available as the alternate function after remap [AFR5]. |
| 31 | PE7/AIN8 | bidirectional | Port E7 I/O with ADC analog input AIN8, slow output speed O1. |
| 32 | PE6/AIN9 | bidirectional | Port E6 I/O with ADC analog input AIN9, slow output speed O1. |
| 33 | PE5/SPI_NSS | bidirectional | Port E5 I/O with SPI master/slave select (SPI_NSS) as default alternate function, slow output speed O1. |
| 34 | PC1/TIM1_CH1 | bidirectional | Port C1 I/O with Timer 1 channel 1 as default alternate function; high-sink capable (HS). |
| 35 | PC2/TIM1_CH2 | bidirectional | Port C2 I/O with Timer 1 channel 2 as default alternate function; high-sink capable (HS). |
| 36 | PC3/TIM1_CH3 | bidirectional | Port C3 I/O with Timer 1 channel 3 as default alternate function; high-sink capable (HS). |
| 37 | PC4/TIM1_CH4 | bidirectional | Port C4 I/O with Timer 1 channel 4 as default alternate function; high-sink capable (HS). |
| 38 | PC5/SPI_SCK | bidirectional | Port C5 I/O with SPI clock as default alternate function; high-sink capable (HS). |
| 39 | VSSIO_2 | power_in | I/O ground for the I/O ring. |
| 40 | VDDIO_2 | power_in | I/O power supply. |
| 41 | PC6/SPI_MOSI | bidirectional | Port C6 I/O with SPI master out / slave in as default alternate function; high-sink capable (HS). |
| 42 | PC7/SPI_MISO | bidirectional | Port C7 I/O with SPI master in / slave out as default alternate function; high-sink capable (HS). |
| 43 | PG0/CAN_TX | bidirectional | Port G0 I/O; the beCAN transmit function is stated to be available on STM8S208xx devices only, so on this STM8S207 device the pin is general-purpose I/O. |
| 44 | PG1/CAN_RX | bidirectional | Port G1 I/O; the beCAN receive function is stated to be available on STM8S208xx devices only, so on this STM8S207 device the pin is general-purpose I/O. |
| 45 | PG2 | bidirectional | Port G2 general-purpose I/O, slow output speed O1. |
| 46 | PG3 | bidirectional | Port G3 general-purpose I/O, slow output speed O1. |
| 47 | PG4 | bidirectional | Port G4 general-purpose I/O, slow output speed O1. |
| 48 | PI0 | bidirectional | Port I0 general-purpose I/O, slow output speed O1. |
| 49 | PG5 | bidirectional | Port G5 general-purpose I/O, slow output speed O1. |
| 50 | PG6 | bidirectional | Port G6 general-purpose I/O, slow output speed O1. |
| 51 | PG7 | bidirectional | Port G7 general-purpose I/O, slow output speed O1. |
| 52 | PE4 | bidirectional | Port E4 general-purpose I/O, slow output speed O1. |
| 53 | PE3/TIM1_BKIN | bidirectional | Port E3 I/O with Timer 1 break input (TIM1_BKIN) as alternate function, slow output speed O1. |
| 54 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain I/O (T; no P-buffer and no protection diode to VDD) carrying the I2C data line I2C_SDA. |
| 55 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain I/O (T; no P-buffer and no protection diode to VDD) carrying the I2C clock line I2C_SCL. |
| 56 | PE0/CLK_CCO | bidirectional | Port E0 I/O with configurable clock output (CLK_CCO) as default alternate function; high-sink capable (HS). |
| 57 | PD0/TIM3_CH2 | bidirectional | Port D0 I/O with Timer 3 channel 2 as default alternate function; high-sink capable (HS), with TIM1_BKIN [AFR3] and CLK_CCO [AFR2] as remap options. |
| 58 | PD1/SWIM | bidirectional | Port D1 I/O with SWIM data interface as default alternate function; high-sink capable (HS), and the pin is in input pull-up during reset and after internal reset release. |
| 59 | PD2/TIM3_CH1 | bidirectional | Port D2 I/O with Timer 3 channel 1 as default alternate function; high-sink capable (HS), with TIM2_CH3 [AFR1] as remap option. |
| 60 | PD3/TIM2_CH2 | bidirectional | Port D3 I/O with Timer 2 channel 2 as default alternate function; high-sink capable (HS), with ADC_ETR [AFR0] as remap option. |
| 61 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 I/O with Timer 2 channel 1 as default alternate function; high-sink capable (HS), with BEEP output [AFR7] as remap option. |
| 62 | PD5/UART3_TX | bidirectional | Port D5 I/O with UART3 data transmit as default alternate function, slow output speed O1. |
| 63 | PD6/UART3_RX | bidirectional | Port D6 I/O with UART3 data receive as default alternate function; the ROM bootloader pulls this pin up during activation before returning it to floating. |
| 64 | PD7/TLI | bidirectional | Port D7 I/O with top level interrupt (TLI) as default alternate function; the TIM1_CH4 remap option [AFR4] is reserved on this package and must be kept at 0. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `STM8S207RBT6CTR`
- Footprint: `Package_QFP:LQFP-64_14x14mm_P0.8mm`
- 3D model: LQFP-64(14x14) (KiCad packages3D, STEP)
- 3D model files: `stm8s207rbt6ctr-etched.step` / `stm8s207rbt6ctr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s207rbt6ctr.step` / `stm8s207rbt6ctr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604434718737772544) (117 pp, sha256 `7adeaa849cf9e22f`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm8s207rbt6ctr-datasheet.pdf)