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STM8S207MBT6BTR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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STM8S207MBT6BTR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-80(14x14)

STM8S207MBT6BTR from STMicroelectronics, in a LQFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Active-low reset pin (I/O in the pin table); the datasheet gives the reset pin electrical limits in section 10.3.7.
2 PA1/OSCIN bidirectional Port A1, I/O with crystal/resonator input (OSCIN), with high-sink not available; port has floating/weak pull-up options.
3 PA2/OSCOUT bidirectional Port A2, I/O with crystal/resonator output (OSCOUT).
4 VSSIO_1 power_in I/O ground.
5 VSS power_in Digital ground.
6 VCAP power_out 1.8 V regulator capacitor connection; the external VCAP capacitor is specified in section 10.3.1.
7 VDD power_in Digital power supply, 2.95 V to 5.5 V operating voltage.
8 VDDIO_1 power_in I/O power supply.
9 PA3/TIM2_CH3 bidirectional Port A3, timer 2 channel 3 (default); alternate function TIM3_CH1 available after AFR1 remap.
10 PA4/UART1_RX bidirectional Port A4, high-sink I/O (HS) with UART1 receive; its default state is controlled by the ROM bootloader (pulled up during bootloader activation, returned to floating before bootloader exit).
11 PA5/UART1_TX bidirectional Port A5, high-sink I/O (HS) with UART1 transmit.
12 PA6/UART1_CK bidirectional Port A6, high-sink I/O (HS) with UART1 synchronous clock.
13 PH0 bidirectional Port H0, high-sink I/O (HS), general purpose.
14 PH1 bidirectional Port H1, high-sink I/O (HS), general purpose.
15 PH2 bidirectional Port H2, general purpose I/O.
16 PH3 bidirectional Port H3, general purpose I/O.
17 PF7/AIN15 bidirectional Port F7, general purpose I/O, ADC analog input 15.
18 PF6/AIN14 bidirectional Port F6, general purpose I/O, ADC analog input 14.
19 PF5/AIN13 bidirectional Port F5, general purpose I/O, ADC analog input 13.
20 PF4/AIN12 bidirectional Port F4, general purpose I/O, ADC analog input 12.
21 PF3/AIN11 bidirectional Port F3, general purpose I/O, ADC analog input 11.
22 VREF+ power_in ADC positive reference voltage.
23 VDDA power_in Analog power supply.
24 VSSA power_in Analog ground.
25 VREF- power_in ADC negative reference voltage.
26 PF0/AIN10 bidirectional Port F0, general purpose I/O, ADC analog input 10.
27 PB7/AIN7 bidirectional Port B7, general purpose I/O, ADC analog input 7.
28 PB6/AIN6 bidirectional Port B6, general purpose I/O, ADC analog input 6.
29 PB5/AIN5 bidirectional Port B5, general purpose I/O, ADC analog input 5; alternate function I2C_SDA after AFR6 remap.
30 PB4/AIN4 bidirectional Port B4, general purpose I/O, ADC analog input 4; alternate function I2C_SCL after AFR6 remap.
31 PB3/AIN3 bidirectional Port B3, general purpose I/O, ADC analog input 3; alternate function TIM1_ETR after AFR5 remap.
32 PB2/AIN2 bidirectional Port B2, general purpose I/O, ADC analog input 2; alternate function TIM1_CH3N after AFR5 remap.
33 PB1/AIN1 bidirectional Port B1, general purpose I/O, ADC analog input 1; alternate function TIM1_CH2N after AFR5 remap.
34 PB0/AIN0 bidirectional Port B0, general purpose I/O, ADC analog input 0; alternate function TIM1_CH1N after AFR5 remap.
35 PH4/TIM1_ETR bidirectional Port H4, general purpose I/O, timer 1 external trigger input.
36 PH5/TIM1_CH3N bidirectional Port H5, general purpose I/O, timer 1 inverted channel 3.
37 PH6/TIM1_CH2N bidirectional Port H6, general purpose I/O, timer 1 inverted channel 2.
38 PH7/TIM1_CH1N bidirectional Port H7, general purpose I/O, timer 1 inverted channel 1.
39 PE7/AIN8 bidirectional Port E7, general purpose I/O, ADC analog input 8.
40 PE6/AIN9 bidirectional Port E6, general purpose I/O, ADC analog input 9.
41 PE5/SPI_NSS bidirectional Port E5, general purpose I/O, SPI master/slave select.
42 PC0/ADC_ETR bidirectional Port C0, general purpose I/O, ADC trigger input.
43 PC1/TIM1_CH1 bidirectional Port C1, high-sink I/O (HS), timer 1 channel 1.
44 PC2/TIM1_CH2 bidirectional Port C2, high-sink I/O (HS), timer 1 channel 2.
45 PC3/TIM1_CH3 bidirectional Port C3, high-sink I/O (HS), timer 1 channel 3.
46 PC4/TIM1_CH4 bidirectional Port C4, high-sink I/O (HS), timer 1 channel 4.
47 PC5/SPI_SCK bidirectional Port C5, high-sink I/O (HS), SPI clock.
48 VSSIO_2 power_in I/O ground.
49 VDDIO_2 power_in I/O power supply.
50 PC6/SPI_MOSI bidirectional Port C6, high-sink I/O (HS), SPI master out / slave in.
51 PC7/SPI_MISO bidirectional Port C7, high-sink I/O (HS), SPI master in / slave out.
52 PG0/CAN_TX bidirectional Port G0, general purpose I/O, beCAN transmit; the beCAN interface is available on STM8S208xx devices only.
53 PG1/CAN_RX bidirectional Port G1, general purpose I/O, beCAN receive; the beCAN interface is available on STM8S208xx devices only.
54 PG2 bidirectional Port G2, general purpose I/O.
55 PG3 bidirectional Port G3, general purpose I/O.
56 PG4 bidirectional Port G4, general purpose I/O.
57 PI0 bidirectional Port I0, general purpose I/O.
58 PI1 bidirectional Port I1, general purpose I/O.
59 PI2 bidirectional Port I2, general purpose I/O.
60 PI3 bidirectional Port I3, general purpose I/O.
61 PI4 bidirectional Port I4, general purpose I/O.
62 PI5 bidirectional Port I5, general purpose I/O.
63 PG5 bidirectional Port G5, general purpose I/O.
64 PG6 bidirectional Port G6, general purpose I/O.
65 PG7 bidirectional Port G7, general purpose I/O.
66 PE4 bidirectional Port E4, general purpose I/O.
67 PE3/TIM1_BKIN bidirectional Port E3, general purpose I/O, timer 1 break input.
68 PE2/I2C_SDA bidirectional Port E2, true open-drain I/O (T; P-buffer, weak pull-up and protection diode to VDD not implemented), I2C data.
69 PE1/I2C_SCL bidirectional Port E1, true open-drain I/O (T; P-buffer, weak pull-up and protection diode to VDD not implemented), I2C clock.
70 PE0/CLK_CCO bidirectional Port E0, high-sink I/O (HS), configurable clock output.
71 PI6 bidirectional Port I6, general purpose I/O.
72 PI7 bidirectional Port I7, general purpose I/O.
73 PD0/TIM3_CH2 bidirectional Port D0, high-sink I/O (HS), timer 3 channel 2; alternate functions TIM1_BKIN (AFR3) and CLK_CCO (AFR2) after remap.
74 PD1/SWIM bidirectional Port D1, high-sink I/O (HS), SWIM data interface; the pin is in input pull-up during the reset phase and after internal reset release.
75 PD2/TIM3_CH1 bidirectional Port D2, high-sink I/O (HS), timer 3 channel 1; alternate function TIM2_CH3 after AFR1 remap.
76 PD3/TIM2_CH2 bidirectional Port D3, high-sink I/O (HS), timer 2 channel 2; alternate function ADC_ETR after AFR0 remap.
77 PD4/TIM2_CH1/BEEP bidirectional Port D4, high-sink I/O (HS), timer 2 channel 1; BEEP output after AFR7 remap.
78 PD5/UART3_TX bidirectional Port D5, general purpose I/O, UART3 data transmit.
79 PD6/UART3_RX bidirectional Port D6, general purpose I/O, UART3 data receive; the default state is controlled by the ROM bootloader (pulled up during bootloader activation, returned to floating before bootloader exit).
80 PD7/TLI bidirectional Port D7, general purpose I/O, top level interrupt input; the TIM1_CH4 remap (AFR4) is listed for this pin but the datasheet states AFR4 is available in the 44-pin package only.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-80(14x14)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: STM8S207MBT6BTR
  • Footprint: Package_QFP:LQFP-80_14x14mm_P0.65mm
  • 3D model: LQFP-80(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm8s207mbt6btr-etched.step / stm8s207mbt6btr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s207mbt6btr.step / stm8s207mbt6btr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 7adeaa849cf9e22f, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF