component
STM8S207MBT6B
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8S207MBT6B
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-80(14x14)
STM8S207MBT6B from STMicroelectronics, in a LQFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | input | Reset input pin with internal pull-up |
| 2 | PA1/OSCIN | bidirectional | Port A1, oscillator input for crystal resonator or external clock input |
| 3 | PA2/OSCOUT | bidirectional | Port A2, oscillator output for crystal resonator feedback network |
| 4 | VSSIO_1 | power_in | I/O ground reference voltage |
| 5 | VSS | power_in | Digital ground reference voltage |
| 6 | VCAP | passive | External capacitor pin for 1.8 V internal voltage regulator |
| 7 | VDD | power_in | Digital power supply voltage, 2.95 to 5.5 V |
| 8 | VDDIO_1 | power_in | I/O power supply voltage |
| 9 | PA3/TIM2_CH3 | output | Port A3, alternate function timer 2 channel 3 output |
| 10 | PA4/UART1_RX | input | Port A4, UART1 receive input pin with high sink capability |
| 11 | PA5/UART1_TX | output | Port A5, UART1 transmit output pin with high sink capability |
| 12 | PA6/UART1_CK | output | Port A6, UART1 synchronous clock output pin with high sink capability |
| 13 | PH0 | bidirectional | Port H0 GPIO pin with high sink output capability |
| 14 | PH1 | bidirectional | Port H1 GPIO pin with high sink output capability |
| 15 | PH2 | bidirectional | Port H2 GPIO pin |
| 16 | PH3 | bidirectional | Port H3 GPIO pin |
| 17 | PF7/AIN15 | input | Port F7, analog input channel 15 |
| 18 | PF6/AIN14 | input | Port F6, analog input channel 14 |
| 19 | PF5/AIN13 | input | Port F5, analog input channel 13 |
| 20 | PF4/AIN12 | input | Port F4, analog input channel 12 |
| 21 | PF3/AIN11 | input | Port F3, analog input channel 11 |
| 22 | VREF+ | power_in | ADC positive reference voltage |
| 23 | VDDA | power_in | Analog power supply voltage |
| 24 | VSSA | power_in | Analog ground reference voltage |
| 25 | VREF- | power_in | ADC negative reference voltage |
| 26 | PF0/AIN10 | input | Port F0, analog input channel 10 |
| 27 | PB7/AIN7 | input | Port B7, analog input channel 7 |
| 28 | PB6/AIN6 | input | Port B6, analog input channel 6 |
| 29 | PB5/AIN5 | input | Port B5, analog input channel 5, alternate function I2C_SDA |
| 30 | PB4/AIN4 | input | Port B4, analog input channel 4, alternate function I2C_SCL |
| 31 | PB3/AIN3 | input | Port B3, analog input channel 3, alternate function TIM1_ETR |
| 32 | PB2/AIN2 | input | Port B2, analog input channel 2 |
| 33 | PB1/AIN1 | input | Port B1, analog input channel 1 |
| 34 | PB0/AIN0 | input | Port B0, analog input channel 0 |
| 35 | PH4/TIM1_ETR | input | Port H4, timer 1 external trigger input |
| 36 | PH5/TIM1_CH3N | output | Port H5, timer 1 inverted channel 3 output |
| 37 | PH6/TIM1_CH2N | output | Port H6, timer 1 inverted channel 2 output |
| 38 | PH7/TIM1_CH1N | output | Port H7, timer 1 inverted channel 1 output |
| 39 | PE7/AIN8 | input | Port E7, analog input channel 8 |
| 40 | PE6/AIN9 | input | Port E6, analog input channel 9 |
| 41 | PE5/SPI_NSS | output | Port E5, SPI chip select slave select output |
| 42 | PC0/ADC_ETR | input | Port C0, ADC external trigger input |
| 43 | PC1/TIM1_CH1 | output | Port C1, timer 1 channel 1 output with high sink capability |
| 44 | PC2/TIM1_CH2 | output | Port C2, timer 1 channel 2 output with high sink capability |
| 45 | PC3/TIM1_CH3 | output | Port C3, timer 1 channel 3 output with high sink capability |
| 46 | PC4/TIM1_CH4 | output | Port C4, timer 1 channel 4 output with high sink capability |
| 47 | PC5/SPI_SCK | output | Port C5, SPI clock output with high sink capability |
| 48 | VSSIO_2 | power_in | I/O ground reference voltage |
| 49 | VDDIO_2 | power_in | I/O power supply voltage |
| 50 | PC6/SPI_MOSI | output | Port C6, SPI master out slave in output with high sink capability |
| 51 | PC7/SPI_MISO | input | Port C7, SPI master in slave out input with high sink capability |
| 52 | PG0/CAN_TX | output | Port G0, beCAN transmit output available on STM8S208xx devices only |
| 53 | PG1/CAN_RX | input | Port G1, beCAN receive input available on STM8S208xx devices only |
| 54 | PG2 | bidirectional | Port G2 GPIO pin |
| 55 | PG3 | bidirectional | Port G3 GPIO pin |
| 56 | PG4 | bidirectional | Port G4 GPIO pin |
| 57 | PI0 | bidirectional | Port I0 GPIO pin |
| 58 | PI1 | bidirectional | Port I1 GPIO pin |
| 59 | PI2 | bidirectional | Port I2 GPIO pin |
| 60 | PI3 | bidirectional | Port I3 GPIO pin |
| 61 | PI4 | bidirectional | Port I4 GPIO pin |
| 62 | PI5 | bidirectional | Port I5 GPIO pin |
| 63 | PG5 | bidirectional | Port G5 GPIO pin |
| 64 | PG6 | bidirectional | Port G6 GPIO pin |
| 65 | PG7 | bidirectional | Port G7 GPIO pin |
| 66 | PE4 | bidirectional | Port E4 GPIO pin |
| 67 | PE3/TIM1_BKIN | input | Port E3, timer 1 break input |
| 68 | PE2/I2C_SDA | tri_state | Port E2, I2C data line with true open-drain output |
| 69 | PE1/I2C_SCL | tri_state | Port E1, I2C clock line with true open-drain output |
| 70 | PE0/CLK_CCO | output | Port E0, configurable clock output with high sink capability |
| 71 | PI6 | bidirectional | Port I6 GPIO pin |
| 72 | PI7 | bidirectional | Port I7 GPIO pin |
| 73 | PD0/TIM3_CH2 | output | Port D0, timer 3 channel 2 output with high sink capability |
| 74 | PD1/SWIM | input | Port D1, single wire interface module debug data pin with input pull-up |
| 75 | PD2/TIM3_CH1 | output | Port D2, timer 3 channel 1 output with high sink capability |
| 76 | PD3/TIM2_CH2 | output | Port D3, timer 2 channel 2 output with high sink capability |
| 77 | PD4/TIM2_CH1 | output | Port D4, timer 2 channel 1 output or beeper output with high sink capability |
| 78 | PD5/UART3_TX | output | Port D5, UART3 transmit output |
| 79 | PD6/UART3_RX | input | Port D6, UART3 receive input |
| 80 | PD7/TLI | input | Port D7, top level interrupt input |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-80(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
CAD (KiCad official)
- Symbol:
STM8S207MBT6B - Footprint:
Package_QFP:LQFP-80_14x14mm_P0.65mm - 3D model: LQFP-80(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm8s207mbt6b-etched.step/stm8s207mbt6b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s207mbt6b.step/stm8s207mbt6b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (103 pp, sha256
9ab3f7b6dda7af91, retrieved 2026-10-01, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).