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STM8S207K6T6C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8S207K6T6C
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STM8S207K6T6C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin with internal pull-up 30-80 kΩ; filtered input pulse < 75 ns ignored; output reset pulse minimum 15 µs; VIL max 0.3×VDD, VIH min 0.7×VDD. |
| 2 | PA1/OSCIN | bidirectional | Port A bit 1; primary alternate function is HSE crystal/resonator oscillator input accepting 1-24 MHz; configurable as external user clock input via OPT4.EXTCLK. |
| 3 | PA2/OSCOUT | bidirectional | Port A bit 2; primary alternate function is HSE crystal/resonator oscillator output; unused when external user clock mode is selected. |
| 4 | VSS | power_in | Digital ground reference; all VSS and VSSA must be within 50 mV of each other. |
| 5 | VCAP | passive | External decoupling capacitor pin for the on-chip 1.8 V main voltage regulator; requires 470-3300 nF with ESR ≤ 0.3 Ω and ESL ≤ 15 nH at 1 MHz. |
| 6 | VDD | power_in | Digital core power supply; operating range 2.95-5.5 V; total source current maximum 60 mA. |
| 7 | VDDIO | power_in | I/O power supply for all I/O ports on the 32-pin package (single VDDIO); operating range 2.95-5.5 V; total I/O output current sum maximum 100 mA source / 80 mA sink. |
| 8 | PF4/AIN12 | bidirectional | Port F bit 4; default alternate function is ADC2 analog input channel 12; input voltage range 0 to VDDA; O1 output speed (up to 2 MHz). |
| 9 | VDDA | power_in | Analog power supply for ADC2; operating range 3-5.5 V; must be connected even when ADC not used. |
| 10 | VSSA | power_in | Analog ground for ADC2; all ground pins must be within 50 mV of each other. |
| 11 | PB5/AIN5 | bidirectional | Port B bit 5; default alternate function ADC2 analog input 5 (0 to VDDA); remappable to I2C_SDA via AFR6 option bit. |
| 12 | PB4/AIN4 | bidirectional | Port B bit 4; default alternate function ADC2 analog input 4 (0 to VDDA); remappable to I2C_SCL via AFR6 option bit. |
| 13 | PB3/AIN3 | bidirectional | Port B bit 3; default alternate function ADC2 analog input 3 (0 to VDDA); remappable to TIM1_ETR external trigger input via AFR5 option bit. |
| 14 | PB2/AIN2 | bidirectional | Port B bit 2; default alternate function ADC2 analog input 2 (0 to VDDA); remappable to TIM1_CH3N complementary output via AFR5 option bit. |
| 15 | PB1/AIN1 | bidirectional | Port B bit 1; default alternate function ADC2 analog input 1 (0 to VDDA); remappable to TIM1_CH2N complementary output via AFR5 option bit. |
| 16 | PB0/AIN0 | bidirectional | Port B bit 0; default alternate function ADC2 analog input 0 (0 to VDDA); remappable to TIM1_CH1N complementary output via AFR5 option bit. |
| 17 | PE5/SPI_NSS | bidirectional | Port E bit 5; default alternate function SPI master/slave select input/output; O1 output speed (up to 2 MHz). |
| 18 | PC1/TIM1_CH1 | bidirectional | Port C bit 1 with high-sink capability; default alternate function TIM1 capture/compare channel 1; O3 output speed (fast/slow programmable, slow after reset). |
| 19 | PC2/TIM1_CH2 | bidirectional | Port C bit 2 with high-sink capability; default alternate function TIM1 capture/compare channel 2; O3 output speed (fast/slow programmable, slow after reset). |
| 20 | PC3/TIM1_CH3 | bidirectional | Port C bit 3 with high-sink capability; default alternate function TIM1 capture/compare channel 3; O3 output speed (fast/slow programmable, slow after reset). |
| 21 | PC4/TIM1_CH4 | bidirectional | Port C bit 4 with high-sink capability; default alternate function TIM1 capture/compare channel 4; O3 output speed (fast/slow programmable, slow after reset). |
| 22 | PC5/SPI_SCK | bidirectional | Port C bit 5 with high-sink capability; default alternate function SPI clock up to 10 Mbit/s (fMASTER/2 master, 6 MHz slave); O3 output speed. |
| 23 | PC6/SPI_MOSI | bidirectional | Port C bit 6 with high-sink capability; default alternate function SPI master-out/slave-in data line; O3 output speed. |
| 24 | PC7/SPI_MISO | bidirectional | Port C bit 7 with high-sink capability; default alternate function SPI master-in/slave-out data line; O3 output speed. |
| 25 | PD0/TIM3_CH2 | bidirectional | Port D bit 0 with high-sink capability; default alternate function TIM3 channel 2; remappable to TIM1_BKIN [AFR3] or CLK_CCO configurable clock output [AFR2] (AFR2 takes priority); O3 output speed. |
| 26 | PD1/SWIM | bidirectional | Port D bit 1 with high-sink capability; default alternate function SWIM single-wire interface module for debug and programming at up to 145 bytes/ms; input pull-up active during reset phase and after reset release; O4 output speed (fast after reset). |
| 27 | PD2/TIM3_CH1 | bidirectional | Port D bit 2 with high-sink capability; default alternate function TIM3 channel 1; remappable to TIM2_CH3 via AFR1 option bit; O3 output speed. |
| 28 | PD3/TIM2_CH2 | bidirectional | Port D bit 3 with high-sink capability; default alternate function TIM2 channel 2; remappable to ADC_ETR external trigger via AFR0 option bit; O3 output speed. |
| 29 | PD4/TIM2_CH1 | bidirectional | Port D bit 4 with high-sink capability; default alternate function TIM2 channel 1; remappable to BEEP output (1/2/4 kHz) via AFR7 option bit; O3 output speed. |
| 30 | PD5/UART3_TX | bidirectional | Port D bit 5; default alternate function UART3 data transmit up to 1 Mbit/s with LIN 2.1 master/slave capability; O1 output speed. |
| 31 | PD6/UART3_RX | bidirectional | Port D bit 6; default alternate function UART3 data receive up to 1 Mbit/s; pin default state is controlled by ROM bootloader (pulled up during bootloader activation, returned to floating before bootloader exit); O1 output speed. |
| 32 | PD7/TLI | bidirectional | Port D bit 7; default alternate function top-level external interrupt (TLI) on dedicated vector; AFR4 remap to TIM1_CH4 is reserved on 32-pin package and must be kept 0; O1 output speed. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
STM8S207K6T6C - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm8s207k6t6c-etched.step/stm8s207k6t6c-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s207k6t6c.step/stm8s207k6t6c.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (117 pp, sha256
7adeaa849cf9e22f, retrieved 2026-09-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).