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STM8S105S6T6C

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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STM8S105S6T6C

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)

STM8S105S6T6C from STMicroelectronics, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Reset input/output pin of the device.
2 PA1/OSCIN bidirectional Port A1 I/O (O1 slow output, wpu, ext. interrupt) that is the resonator/crystal input.
3 PA2/OSCOUT bidirectional Port A2 I/O (O1 slow output, wpu, ext. interrupt) that is the resonator/crystal output.
4 VSSIO_1 power_in I/O ground.
5 VSS power_in Digital ground.
6 VCAP passive Connection for the 1.8 V regulator capacitor.
7 VDD power_in Digital power supply (2.95 V to 5.5 V operating voltage).
8 VDDIO_1 power_in I/O power supply.
9 PA4 bidirectional Port A4 I/O with high sink capability (O3 output, wpu, ext. interrupt).
10 PA5 bidirectional Port A5 I/O with high sink capability (O3 output, wpu, ext. interrupt).
11 PA6 bidirectional Port A6 I/O with high sink capability (O3 output, wpu, ext. interrupt).
12 VDDA power_in Analog power supply.
13 VSSA power_in Analog ground.
14 PB7/AIN7 bidirectional Port B7 I/O (O1 output, wpu, ext. interrupt) with analog input 7.
15 PB6/AIN6 bidirectional Port B6 I/O (O1 output, wpu, ext. interrupt) with analog input 6.
16 PB5/AIN5 bidirectional Port B5 I/O with analog input 5; I2C_SDA via AFR6 remap.
17 PB4/AIN4 bidirectional Port B4 I/O with analog input 4; I2C_SCL via AFR6 remap.
18 PB3/AIN3 bidirectional Port B3 I/O with analog input 3; TIM1_ETR via AFR5 remap.
19 PB2/AIN2 bidirectional Port B2 I/O with analog input 2; TIM1_CH3N via AFR5 remap.
20 PB1/AIN1 bidirectional Port B1 I/O with analog input 1; TIM1_CH2N via AFR5 remap.
21 PB0/AIN0 bidirectional Port B0 I/O with analog input 0; TIM1_CH1N via AFR5 remap.
22 PE6/AIN9 bidirectional Port E6 I/O with analog input 9, which cannot be used by ADC scan mode in the 44-pin package.
23 PE5/SPI_NSS bidirectional Port E5 I/O (O1 output, wpu, ext. interrupt) that is the SPI master/slave select.
24 PC1/TIM1_CH1/UART2_CK bidirectional Port C1 high sink I/O (O3) that is Timer 1 channel 1 and UART2 synchronous clock.
25 PC2/TIM1_CH2 bidirectional Port C2 high sink I/O (O3) that is Timer 1 channel 2.
26 PC3/TIM1_CH3 bidirectional Port C3 high sink I/O (O3) that is Timer 1 channel 3.
27 PC5/SPI_SCK bidirectional Port C5 high sink I/O (O3) that is the SPI clock.
28 VSSIO_2 power_in I/O ground.
29 VDDIO_2 power_in I/O power supply.
30 PC6/SPI_MOSI bidirectional Port C6 high sink I/O (O3) that is SPI master out/slave in.
31 PC7/SPI_MISO bidirectional Port C7 high sink I/O (O3) that is SPI master in/slave out.
32 PG0 bidirectional Port G0 general purpose I/O (O1 output, wpu, ext. interrupt).
33 PG1 bidirectional Port G1 general purpose I/O (O1 output, wpu, ext. interrupt).
34 PE2/I2C_SDA bidirectional Port E2 true open-drain I/O that is the I2C data line.
35 PE1/I2C_SCL bidirectional Port E1 true open-drain I/O that is the I2C clock line.
36 PE0/CLK_CCO bidirectional Port E0 high sink I/O (O3) that is the configurable clock output.
37 PD0/TIM3_CH2 bidirectional Port D0 high sink I/O (O3) that is Timer 3 channel 2; TIM1_BKIN via AFR3 or CLK_CCO via AFR2 remap.
38 PD1/SWIM bidirectional Port D1 high sink I/O (O4) that is the SWIM data interface, in input pull-up during and after reset.
39 PD2/TIM3_CH1 bidirectional Port D2 high sink I/O (O3) that is Timer 3 channel 1; TIM2_CH3 via AFR1 remap.
40 PD3/TIM2_CH2 bidirectional Port D3 high sink I/O (O3) that is Timer 2 channel 2; ADC_ETR via AFR0 remap.
41 PD4/TIM2_CH1 bidirectional Port D4 high sink I/O (O3) that is Timer 2 channel 1; BEEP output via AFR7 remap.
42 PD5/UART2_TX bidirectional Port D5 I/O (O1 output) that is UART2 data transmit.
43 PD6/UART2_RX bidirectional Port D6 I/O (O1 output) that is UART2 data receive.
44 PD7/TLI bidirectional Port D7 I/O (O1 output) that is the top level interrupt input; TIM1_CH4 via AFR4 remap.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

CAD (KiCad official)

  • Symbol: STM8S105S6T6C
  • Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
  • 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm8s105s6t6c-etched.step / stm8s105s6t6c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s105s6t6c.step / stm8s105s6t6c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (124 pp, sha256 fe32941a395f42c2, retrieved 2026-09-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF