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STM8S105K6T6C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8S105K6T6C
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STM8S105K6T6C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin: internal pull-up (RPU 30-80 kΩ), drive low (VIL(NRST) max 0.3xVDD) to force an external reset, or the pin is driven low as an output during internal reset; minimum recommended external capacitor 100 nF. |
| 2 | PA1/OSCIN | bidirectional | General-purpose I/O port A1 (floating/weak pull-up, output speed O1 up to 2 MHz), alternate function high-speed external crystal/resonator oscillator input or user external clock input (OSC_IN), 1-16 MHz. |
| 3 | PA2/OSCOUT | bidirectional | General-purpose I/O port A2 (floating/weak pull-up, output speed O1 up to 2 MHz), alternate function high-speed external crystal/resonator oscillator output (OSC_OUT). |
| 4 | VSS | power_in | Digital ground supply pin, referenced to 0 V for the digital core and I/O. |
| 5 | VCAP | power_out | Internal 1.8 V main voltage regulator output; requires an external stabilization capacitor CEXT (470 nF to 3300 nF, ESR ≤0.3 Ω at 1 MHz, ESL ≤15 nH) connected to VSS. |
| 6 | VDD | power_in | Digital power supply pin, operating voltage range 2.95 V to 5.5 V. |
| 7 | VDDIO_1 | power_in | I/O power supply pin for the associated port pins, 2.95 V to 5.5 V. |
| 8 | PF4/AIN12 | bidirectional | General-purpose I/O port F4 with pull-up applied during reset (floating input after reset release, output speed O1), alternate function ADC analog input AIN12; AIN12 is not selectable in ADC scan mode or with the analog watchdog and is stored only in ADC_DRH/DRL. |
| 9 | VDDA | power_in | Analog power supply pin for the ADC and analog blocks, 3.0 V to 5.5 V. |
| 10 | VSSA | power_in | Analog ground supply pin. |
| 11 | PB5/AIN5[I2C_SDA] | bidirectional | General-purpose I/O port B5 (floating/weak pull-up, output speed O1), default alternate function ADC analog input AIN5, remappable via option bit AFR6 to I2C data line (I2C_SDA). |
| 12 | PB4/AIN4[I2C_SCL] | bidirectional | General-purpose I/O port B4 (floating/weak pull-up, output speed O1), default alternate function ADC analog input AIN4, remappable via option bit AFR6 to I2C clock line (I2C_SCL). |
| 13 | PB3/AIN3[TIM1_ETR] | bidirectional | General-purpose I/O port B3 (floating/weak pull-up, output speed O1), default alternate function ADC analog input AIN3, remappable via option bit AFR5 to TIM1 external trigger input (TIM1_ETR). |
| 14 | PB2/AIN2[TIM1_CH3N] | bidirectional | General-purpose I/O port B2 (floating/weak pull-up, output speed O1), default alternate function ADC analog input AIN2, remappable via option bit AFR5 to TIM1 complementary output channel 3 (TIM1_CH3N). |
| 15 | PB1/AIN1[TIM1_CH2N] | bidirectional | General-purpose I/O port B1 (floating/weak pull-up, output speed O1), default alternate function ADC analog input AIN1, remappable via option bit AFR5 to TIM1 complementary output channel 2 (TIM1_CH2N). |
| 16 | PB0/AIN0[TIM1_CH1N] | bidirectional | General-purpose I/O port B0 (floating/weak pull-up, output speed O1), default alternate function ADC analog input AIN0, remappable via option bit AFR5 to TIM1 complementary output channel 1 (TIM1_CH1N). |
| 17 | PE5/SPI_NSS | bidirectional | General-purpose I/O port E5 (floating/weak pull-up, output speed O1), alternate function SPI master/slave select input (SPI_NSS). |
| 18 | PC1/TIM1_CH1/UART2_CK | bidirectional | General-purpose high-sink I/O port C1 (output speed O3, up to 10 MHz), alternate function TIM1 input capture/output compare channel 1 or UART2 synchronous clock (UART2_CK). |
| 19 | PC2/TIM1_CH2 | bidirectional | General-purpose high-sink I/O port C2 (output speed O3), alternate function TIM1 input capture/output compare channel 2 (TIM1_CH2). |
| 20 | PC3/TIM1_CH3 | bidirectional | General-purpose high-sink I/O port C3 (output speed O3), alternate function TIM1 input capture/output compare channel 3 (TIM1_CH3). |
| 21 | PC4/TIM1_CH4 | bidirectional | General-purpose high-sink I/O port C4 (output speed O3), alternate function TIM1 input capture/output compare channel 4 (TIM1_CH4). |
| 22 | PC5/SPI_SCK | bidirectional | General-purpose high-sink I/O port C5 (output speed O3), alternate function SPI serial clock (SPI_SCK), up to 8 Mbit/s. |
| 23 | PC6/SPI_MOSI | bidirectional | General-purpose high-sink I/O port C6 (output speed O3), alternate function SPI master-out/slave-in data line (SPI_MOSI). |
| 24 | PC7/SPI_MISO | bidirectional | General-purpose high-sink I/O port C7 (output speed O3), alternate function SPI master-in/slave-out data line (SPI_MISO). |
| 25 | PD0/TIM3_CH2[TIM1_BKIN][CLK_CCO] | bidirectional | General-purpose high-sink I/O port D0 (output speed O3), default alternate function TIM3 channel 2, remappable via AFR3 to TIM1 break input (TIM1_BKIN) or via AFR2 to configurable clock output (CLK_CCO); AFR2 has priority over AFR3 if both activated. |
| 26 | PD1/SWIM | bidirectional | Single wire interface module (SWIM) data pin (input pull-up during and after reset release, output speed O4), also usable as high-sink general-purpose I/O port D1; SWIM max transmission speed 145 bytes/ms. |
| 27 | PD2/TIM3_CH1[TIM2_CH3] | bidirectional | General-purpose high-sink I/O port D2 (output speed O3), default alternate function TIM3 channel 1, remappable via option bit AFR1 to TIM2 channel 3 (TIM2_CH3). |
| 28 | PD3/TIM2_CH2[ADC_ETR] | bidirectional | General-purpose high-sink I/O port D3 (output speed O3), default alternate function TIM2 channel 2, remappable via option bit AFR0 to ADC external trigger input (ADC_ETR). |
| 29 | PD4/TIM2_CH1[BEEP] | bidirectional | General-purpose high-sink I/O port D4 (output speed O3), default alternate function TIM2 channel 1, remappable via option bit AFR7 to beeper output (BEEP, 1/2/4 kHz square wave). |
| 30 | PD5/UART2_TX | bidirectional | General-purpose I/O port D5 (output speed O1), alternate function UART2 data transmit (UART2_TX). |
| 31 | PD6/UART2_RX | bidirectional | General-purpose I/O port D6 (output speed O1), alternate function UART2 data receive (UART2_RX). |
| 32 | PD7/TLI[TIM1_CH4] | bidirectional | General-purpose I/O port D7 (output speed O1), default alternate function top-level interrupt input (TLI), remappable via option bit AFR4 to TIM1 channel 4 (TIM1_CH4). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
STM8S105K6T6C - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm8s105k6t6c-etched.step/stm8s105k6t6c-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s105k6t6c.step/stm8s105k6t6c.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (121 pp, sha256
b1007bc27bb78327, retrieved 2026-09-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).