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STM8S105K4U6A

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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STM8S105K4U6A

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)

STM8S105K4U6A from STMicroelectronics, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Bidirectional active-low reset. Weak pull-up input; can be driven low to force a reset and is pulled low by internal reset sources.
2 PA1/OSC_IN bidirectional Port A1 general-purpose I/O. Alternate function: external crystal/resonator oscillator input (OSCIN) for the HSE clock source.
3 PA2/OSC_OUT bidirectional Port A2 general-purpose I/O. Alternate function: external crystal/resonator oscillator output (OSCOUT) for the HSE clock source.
4 VSS power_in Digital ground reference for the MCU core.
5 VCAP passive 1.8 V internal regulator decoupling. Connect a 1 uF ceramic capacitor between this pin and VSS; do not tie to any supply.
6 VDD power_in Digital core supply, 2.95 V to 5.5 V. Must be decoupled to VSS.
7 VDDIO power_in I/O power supply for GPIO drivers, 2.95 V to 5.5 V (VDDIO_1 rail in this package).
8 PF4/AIN12 bidirectional Port F4 general-purpose I/O with weak pull-up applied during reset phase (floating after reset release). Alternate function: ADC analog input channel 12 (not usable in ADC scan mode or with analog watchdog).
9 VDDA power_in Analog supply for the ADC and analog reference. Tie to VDD via a filter for best ADC accuracy.
10 VSSA power_in Analog ground reference for the ADC.
11 PB5/AIN5/[I2C_SDA] bidirectional Port B5 GPIO. Alternate functions: ADC analog input 5 and remapped I2C data (I2C_SDA) when AFR6 option bit is set.
12 PB4/AIN4/[I2C_SCL] bidirectional Port B4 GPIO. Alternate functions: ADC analog input 4 and remapped I2C clock (I2C_SCL) when AFR6 option bit is set.
13 PB3/AIN3/[TIM1_ETR] bidirectional Port B3 GPIO. Alternate functions: ADC analog input 3 and remapped TIM1_ETR external trigger (AFR5 option bit).
14 PB2/AIN2/[TIM1_CH3N] bidirectional Port B2 GPIO. Alternate functions: ADC analog input 2 and remapped TIM1 channel 3 complementary output (AFR5 option bit).
15 PB1/AIN1/[TIM1_CH2N] bidirectional Port B1 GPIO. Alternate functions: ADC analog input 1 and remapped TIM1 channel 2 complementary output (AFR5 option bit).
16 PB0/AIN0/[TIM1_CH1N] bidirectional Port B0 GPIO. Alternate functions: ADC analog input 0 and remapped TIM1 channel 1 complementary output (AFR5 option bit).
17 PE5/SPI_NSS bidirectional Port E5 GPIO. Alternate function: SPI master/slave select (SPI_NSS).
18 PC1/TIM1_CH1/UART2_CK bidirectional Port C1 high-sink GPIO. Alternate functions: TIM1 channel 1 and UART2 synchronous clock (UART2_CK).
19 PC2/TIM1_CH2 bidirectional Port C2 high-sink GPIO. Alternate function: TIM1 channel 2.
20 PC3/TIM1_CH3 bidirectional Port C3 high-sink GPIO. Alternate function: TIM1 channel 3.
21 PC4/TIM1_CH4 bidirectional Port C4 high-sink GPIO. Alternate function: TIM1 channel 4.
22 PC5/SPI_SCK bidirectional Port C5 high-sink GPIO. Alternate function: SPI clock (SPI_SCK).
23 PC6/SPI_MOSI bidirectional Port C6 high-sink GPIO. Alternate function: SPI master-out/slave-in (SPI_MOSI).
24 PC7/SPI_MISO bidirectional Port C7 high-sink GPIO. Alternate function: SPI master-in/slave-out (SPI_MISO).
25 PD0/TIM3_CH2/[TIM1_BKIN]/[CLK_CCO] bidirectional Port D0 high-sink GPIO. Alternate functions: TIM3 channel 2 (default) and, via option bits, TIM1_BKIN (break input, AFR3) or configurable clock output CLK_CCO (AFR2).
26 PD1/SWIM bidirectional Port D1 high-sink GPIO. Alternate function: SWIM single-wire interface for programming and debugging. Pin is in input pull-up during and after reset.
27 PD2/TIM3_CH1/[TIM2_CH3] bidirectional Port D2 high-sink GPIO. Alternate functions: TIM3 channel 1 (default) and TIM2 channel 3 when remapped via AFR1 option bit.
28 PD3/TIM2_CH2/[ADC_ETR] bidirectional Port D3 high-sink GPIO. Alternate functions: TIM2 channel 2 (default) and ADC external trigger (ADC_ETR) when remapped via AFR0 option bit.
29 PD4/TIM2_CH1/[BEEP] bidirectional Port D4 high-sink GPIO. Alternate functions: TIM2 channel 1 (default) and BEEP output when remapped via AFR7 option bit.
30 PD5/UART2_TX bidirectional Port D5 GPIO. Alternate function: UART2 data transmit (UART2_TX).
31 PD6/UART2_RX bidirectional Port D6 GPIO. Alternate function: UART2 data receive (UART2_RX).
32 PD7/TLI/[TIM1_CH4] bidirectional Port D7 GPIO. Alternate functions: top-level interrupt input (TLI) and remapped TIM1 channel 4 (AFR4 option bit).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package QFN-32-EP(5x5)
Category MCU
Pins 32

Ordering variants

Same part, different packaging or reel option.

  • STM8S105K4U6A
  • STM8S105K4U6AK6U6A
  • STM8S105K4U6AK4T6A
  • STM8S105K4U6AK6T6A
  • STM8S105K4U6AS4T6A
  • STM8S105K4U6AS6T6A
  • STM8S105K4U6AC4T6A
  • STM8S105K4U6AC6T6A
  • STM8S105K4U6AK4B6A
  • STM8S105K4U6AK6B6A

CAD (KiCad official)

  • Symbol: STM8S105K4U6A
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: stm8s105k4u6a-etched.step / stm8s105k4u6a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s105k4u6a.step / stm8s105k4u6a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (121 pp, sha256 b1007bc27bb78327, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF