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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM8S105C6T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM8S105C6T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	input	Reset pin with Schmitt trigger input, internal pull-up resistor 30-80 kΩ, filtered pulse width 75 ns minimum.
2	PA1/OSC_IN	bidirectional	Port A1 I/O pin functioning as high-speed external oscillator input or GPIO with weak pull-up.
3	PA2/OSC_OUT	bidirectional	Port A2 I/O pin functioning as high-speed external oscillator output or GPIO with weak pull-up.
4	VSSIO_1	power_in	I/O power supply ground for port bank 1, must be connected to system ground.
5	VSS	power_in	Digital ground for core logic and memory, must be connected to system ground.
6	VCAP	power_in	Internal regulator 1.8V output; requires external 470-3300 nF capacitor with ESR 0.3 Ω and ESL 15 nH maximum.
7	VDD	power_in	Digital power supply, operating voltage range 2.95-5.5 V, must be connected to system power supply.
8	VDDIO_1	power_in	I/O power supply for port bank 1, operating voltage range 2.95-5.5 V.
9	PA3/TIM2_CH3	bidirectional	Port A3 I/O pin with weak pull-up, default function Timer2 channel 3, remappable to Timer3 channel 1 via AFR1.
10	PA4	bidirectional	Port A4 I/O pin with high-sink output capability and weak pull-up, output slew rate programmable.
11	PA5	bidirectional	Port A5 I/O pin with high-sink output capability and weak pull-up, output slew rate programmable.
12	PA6	bidirectional	Port A6 I/O pin with high-sink output capability and weak pull-up, output slew rate programmable.
13	VDDA	power_in	Analog power supply for ADC and analog blocks, operating voltage range 3.0-5.5 V.
14	VSSA	power_in	Analog ground reference for ADC and analog circuits, must be connected to system ground.
15	PB7/AIN7	bidirectional	Port B7 I/O pin functioning as analog input channel AIN7 with weak pull-up when used as GPIO.
16	PB6/AIN6	bidirectional	Port B6 I/O pin functioning as analog input channel AIN6 with weak pull-up when used as GPIO.
17	PB5/AIN5	bidirectional	Port B5 I/O pin functioning as analog input AIN5 or remappable to I2C_SDA via AFR6 option bit.
18	PB4/AIN4	bidirectional	Port B4 I/O pin functioning as analog input AIN4 or remappable to I2C_SCL via AFR6 option bit.
19	PB3/AIN3	bidirectional	Port B3 I/O pin functioning as analog input AIN3 or remappable to TIM1_ETR via AFR5 option bit.
20	PB2/AIN2	bidirectional	Port B2 I/O pin functioning as analog input AIN2 or remappable to TIM1_CH3N via AFR5 option bit.
21	PB1/AIN1	bidirectional	Port B1 I/O pin functioning as analog input AIN1 or remappable to TIM1_CH2N via AFR5 option bit.
22	PB0/AIN0	bidirectional	Port B0 I/O pin functioning as analog input AIN0 or remappable to TIM1_CH1N via AFR5 option bit.
23	PE7/AIN8	bidirectional	Port E7 I/O pin functioning as analog input channel AIN8 with weak pull-up when used as GPIO.
24	PE6/AIN9	bidirectional	Port E6 I/O pin functioning as analog input channel AIN9 (not available in ADC scan mode for 44-pin package).
25	PE5/SPI_NSS	bidirectional	Port E5 I/O pin functioning as SPI slave select or chip select line for SPI master/slave operation.
26	PC1/TIM1_CH1	bidirectional	Port C1 I/O pin with high-sink output, default function Timer1 channel 1 or UART2 synchronous clock.
27	PC2/TIM1_CH2	bidirectional	Port C2 I/O pin with high-sink output, default function Timer1 channel 2 output.
28	PC3/TIM1_CH3	bidirectional	Port C3 I/O pin with high-sink output, default function Timer1 channel 3 output.
29	PC4/TIM1_CH4	bidirectional	Port C4 I/O pin with high-sink output, default function Timer1 channel 4 output.
30	PC5/SPI_SCK	bidirectional	Port C5 I/O pin with high-sink output, default function SPI serial clock with maximum frequency 8 MHz.
31	VSSIO_2	power_in	I/O power supply ground for port bank 2, must be connected to system ground.
32	VDDIO_2	power_in	I/O power supply for port bank 2, operating voltage range 2.95-5.5 V.
33	PC6/SPI_MOSI	bidirectional	Port C6 I/O pin with high-sink output, default function SPI master out/slave in with maximum frequency 8 MHz.
34	PC7/SPI_MISO	bidirectional	Port C7 I/O pin with high-sink output, default function SPI master in/slave out with maximum frequency 8 MHz.
35	PG0	bidirectional	Port G0 I/O pin with weak pull-up and weak drive current capability.
36	PG1	bidirectional	Port G1 I/O pin with weak pull-up and weak drive current capability.
37	PE3/TIM1_BKIN	bidirectional	Port E3 I/O pin functioning as Timer1 break input for control of complementary PWM outputs.
38	PE2/I2C_SDA	bidirectional	Port E2 true open-drain I/O (P-buffer and pull-up not implemented), default function I2C data line, maximum 400 kbit/s.
39	PE1/I2C_SCL	bidirectional	Port E1 true open-drain I/O (P-buffer and pull-up not implemented), default function I2C clock line, maximum 400 kbit/s.
40	PE0/CLK_CCO	bidirectional	Port E0 I/O pin with high-sink output, default function configurable clock output for external synchronization.
41	PD0/TIM3_CH2	bidirectional	Port D0 I/O pin with high-sink output, default function Timer3 channel 2, remappable to TIM1_BKIN or CLK_CCO via AFR3 or AFR2.
42	PD1/SWIM	bidirectional	Port D1 I/O pin with high-sink output and external interrupt capability, default function SWIM single-wire debug interface data line.
43	PD2/TIM3_CH1	bidirectional	Port D2 I/O pin with high-sink output, default function Timer3 channel 1, remappable to TIM2_CH3 via AFR1.
44	PD3/TIM2_CH2	bidirectional	Port D3 I/O pin with high-sink output, default function Timer2 channel 2, remappable to ADC_ETR via AFR0.
45	PD4/TIM2_CH1	bidirectional	Port D4 I/O pin with high-sink output, default function Timer2 channel 1, remappable to BEEP output via AFR7.
46	PD5/UART2_TX	bidirectional	Port D5 I/O pin functioning as UART2 transmit data output at 1 Mbit/s maximum with weak drive capability.
47	PD6/UART2_RX	bidirectional	Port D6 I/O pin functioning as UART2 receive data input at 1 Mbit/s maximum with weak pull-up.
48	PD7/TLI	bidirectional	Port D7 I/O pin functioning as top-level external interrupt input, remappable to TIM1_CH4 via AFR4.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

CAD (KiCad official)

Symbol: STM8S105C6T6
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm8s105c6t6-etched.step / stm8s105c6t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s105c6t6.step / stm8s105c6t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (121 pp, sha256 b1007bc27bb78327, retrieved 2026-09-24, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF