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STM8S105C6T3

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm8s105c6t3factory-2.0.0extractor-text

Verified STM8S105C6T3

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: STM8S105C6T3 · LQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 121-page datasheet
  • ✓distributor: lcsc C1338699, digikey 497-17916-ND, mouser 511-STM8S105C6T3
  • ✓family: LQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-b11mrf3_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ stm8s105c6t3.kicad_sym✓ stm8s105c6t3.kicad_mod✓ stm8s105c6t3.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers stm8s105c6t3: viewers · Ray 2h ago
package.json Publish 0.1.0 · Ray 2h ago
page.json Set visibility: public · Ray 2h ago
README.md Publish 0.1.0 · Ray 2h ago
stm8s105c6t3-etched.glb Publish 0.1.0 · Ray 2h ago
stm8s105c6t3-etched.step stm8s105c6t3: factory component page (tier=mfr) · Ray 2h ago
stm8s105c6t3-hero.glb stm8s105c6t3: hero GLB from the etched model (keeps the MPN mark) · Ray 2h ago
stm8s105c6t3-hero.overlay.json Publish 0.1.0 · Ray 2h ago
stm8s105c6t3.glb Publish 0.1.0 · Ray 2h ago
stm8s105c6t3.kicad_mod Publish 0.1.0 · Ray 2h ago
stm8s105c6t3.kicad_sym Publish 0.1.0 · Ray 2h ago
stm8s105c6t3.lbr Publish 0.1.0 · Ray 2h ago
stm8s105c6t3.step Publish 0.1.0 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 48 pins · Ray 2h ago

STM8S105C6T3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM8S105C6T3 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Active-low reset pin, input floating after reset release with a reset-phase function as listed in the pin table.
2 PA1/OSCIN bidirectional Port A1 with resonator/crystal oscillator input (OSCIN), slow output speed O1, input floating and weak pull-up available.
3 PA2/OSCOUT bidirectional Port A2 with resonator/crystal oscillator output (OSCOUT), slow output speed O1, input floating and weak pull-up available.
4 VSSIO_1 power_in I/O ground supply pin.
5 VSS power_in Digital ground.
6 VCAP passive 1.8 V regulator capacitor connection; external capacitor required per the VCAP specification.
7 VDD power_in Digital power supply.
8 VDDIO_1 power_in I/O power supply.
9 PA3/TIM2_CH3 [TIM3_CH1] bidirectional Port A3 with Timer 2 channel 3 as default alternate function; TIM3_CH1 available when AFR1 remapping is enabled.
10 PA4 bidirectional Port A4 general-purpose I/O with high sink capability, output speed O3.
11 PA5 bidirectional Port A5 general-purpose I/O with high sink capability, output speed O3.
12 PA6 bidirectional Port A6 general-purpose I/O with high sink capability, output speed O3.
13 VDDA power_in Analog power supply.
14 VSSA power_in Analog ground.
15 PB7/AIN7 bidirectional Port B7 general-purpose I/O with analog input 7 for the ADC.
16 PB6/AIN6 bidirectional Port B6 general-purpose I/O with analog input 6 for the ADC.
17 PB5/AIN5 [I2C_SDA] bidirectional Port B5 with analog input 5; I2C_SDA alternate function available when AFR6 remapping is enabled.
18 PB4/AIN4 [I2C_SCL] bidirectional Port B4 with analog input 4; I2C_SCL alternate function available when AFR6 remapping is enabled.
19 PB3/AIN3 [TIM1_ETR] bidirectional Port B3 with analog input 3; TIM1_ETR alternate function available when AFR5 remapping is enabled.
20 PB2/AIN2 [TIM1_CH3N] bidirectional Port B2 with analog input 2; TIM1_CH3N alternate function available when AFR5 remapping is enabled.
21 PB1/AIN1 [TIM1_CH2N] bidirectional Port B1 with analog input 1; TIM1_CH2N alternate function available when AFR5 remapping is enabled.
22 PB0/AIN0 [TIM1_CH1N] bidirectional Port B0 with analog input 0; TIM1_CH1N alternate function available when AFR5 remapping is enabled.
23 PE7/AIN8 bidirectional Port E7 general-purpose I/O with analog input 8 for the ADC.
24 PE6/AIN9 bidirectional Port E6 general-purpose I/O with analog input 9; in 44-pin package AIN9 cannot be used by ADC scan mode.
25 PE5/SPI_NSS bidirectional Port E5 general-purpose I/O with SPI master/slave select function.
26 PC1/TIM1_CH1/UART2_CK bidirectional Port C1 with high sink capability, output speed O3; TIM1 channel 1 and UART2 synchronous clock alternate functions.
27 PC2/TIM1_CH2 bidirectional Port C2 with high sink capability, output speed O3; TIM1 channel 2 alternate function.
28 PC3/TIM1_CH3 bidirectional Port C3 with high sink capability, output speed O3; TIM1 channel 3 alternate function.
29 PC4/TIM1_CH4 bidirectional Port C4 with high sink capability, output speed O3; TIM1 channel 4 alternate function.
30 PC5/SPI_SCK bidirectional Port C5 with high sink capability, output speed O3; SPI clock alternate function.
31 VSSIO_2 power_in I/O ground supply pin.
32 VDDIO_2 power_in I/O power supply.
33 PC6/SPI_MOSI bidirectional Port C6 with high sink capability, output speed O3; SPI master out/slave in alternate function.
34 PC7/SPI_MISO bidirectional Port C7 with high sink capability, output speed O3; SPI master in/slave out alternate function.
35 PG0 bidirectional Port G0 general-purpose I/O, output speed O1.
36 PG1 bidirectional Port G1 general-purpose I/O, output speed O1.
37 PE3/TIM1_BKIN bidirectional Port E3 general-purpose I/O with Timer 1 break input (TIM1_BKIN) alternate function.
38 PE2/I2C_SDA bidirectional Port E2 with I2C data line as true open-drain I/O (P-buffer and protection diode to VDD not implemented).
39 PE1/I2C_SCL bidirectional Port E1 with I2C clock line as true open-drain I/O (P-buffer and protection diode to VDD not implemented).
40 PE0/CLK_CCO bidirectional Port E0 with high sink capability and configurable clock output (CLK_CCO) alternate function.
41 PD0/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] bidirectional Port D0 with high sink capability; TIM3 channel 2 default, TIM1_BKIN (AFR3) or CLK_CCO (AFR2) available by remapping, with AFR2 taking priority.
42 PD1/SWIM bidirectional Port D1 with high sink capability and SWIM data interface; input pull-up during reset phase and after internal reset release.
43 PD2/TIM3_CH1 [TIM2_CH3] bidirectional Port D2 with high sink capability; Timer 3 channel 1 default, TIM2_CH3 available when AFR1 remapping is enabled.
44 PD3/TIM2_CH2 [ADC_ETR] bidirectional Port D3 with high sink capability; Timer 2 channel 2 default, ADC external trigger (ADC_ETR) available when AFR0 remapping is enabled.
45 PD4/TIM2_CH1 [BEEP] bidirectional Port D4 with high sink capability; Timer 2 channel 1 default, BEEP output available when AFR7 remapping is enabled.
46 PD5/UART2_TX bidirectional Port D5 general-purpose I/O with UART2 data transmit alternate function, output speed O1.
47 PD6/UART2_RX bidirectional Port D6 general-purpose I/O with UART2 data receive alternate function, output speed O1.
48 PD7/TLI [TIM1_CH4] bidirectional Port D7 with top level interrupt (TLI) function; TIM1_CH4 available when AFR4 remapping is enabled.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (including VDDA and VDDIO) VDDx-VSS -0.3 6.5 V 53
Total current into VDD power lines (source) IVDD 100 mA 53
Total current out of VSS ground lines (sink) IVSS 80 mA 53
Output current sunk by any I/O and control pin IIO 20 mA 53
Output current source by any I/O and control pin IIO -20 mA 53
Injected current on any other pin IINJ(PIN) -4 4 mA Injected current on any other pin 53
Storage temperature range TSTG -65 150 °C 54
Maximum junction temperature TJ 150 °C 54
Internal CPU clock frequency fCPU 0 16 MHz 54
Standard operating voltage VDD/VDDIO 2.95 5.5 V 54
CEXT: capacitance of external capacitor VCAP 470 3300 nF CEXT: capacitance of external capacitor 54
ESR of external capacitor at 1 MHz VCAP 0.3 Ω ESR of external capacitor at 1 MHz 54
ESL of external capacitor VCAP 15 nH ESL of external capacitor 54
Power dissipation at TA = 125 °C for suffix 3 PD 443 mW 44- and 48-pin devices, with output on eight standard ports, two high sink ports and two open drain ports simultaneously 54
Ambient temperature for suffix 3 version TA -40 125 °C Ambient temperature for suffix 3 version 54
Junction temperature range, suffix 3 version TJ -40 130 °C Suffix 3 version 55
Operating voltage (all modes, execution/write/erase) VDD 2.95 5.5 V fCPU ≤ 16 MHz 72
Power-on reset threshold VIT+ 2.65 2.8 2.95 V 56
Brown-out reset threshold VIT- 2.58 2.65 2.88 V 56
Brown-out reset hysteresis VHYS(BOR) 70 mV 56
Pull-up resistor Rpu 30 55 80 k VDD = 5 V, VIN = VSS 73
NRST pull-up resistor RPU(NRST) 30 55 80 k 78
NRST output low level voltage VOL(NRST) 0.5 V IOL= 3 mA 78
Output low level with 8 pins sunk (standard ports) VOL 2 V IIO= 10 mA, VDD = 5 V 74
Output high level with 8 pins sourced (standard ports) VOH 2.4 V IIO= 10 mA, VDD = 5 V 74
Output low level with 4 pins sunk (standard ports) VOL 1 V IIO= 4 mA, VDD = 3.3 V 74
Output high level with 4 pins sourced (standard ports) VOH 2 V IIO= 4 mA, VDD = 3.3 V 74
Output low level with 8 pins sunk (high sink ports) VOL 0.9 V IIO= 10 mA, VDD = 5 V 75
Output high level with 8 pins sourced (high sink ports) VOH 3.8 V IIO= 10 mA, VDD = 5 V 75
HSE user external clock source frequency fHSE_ext 0 16 MHz 66
Accuracy of HSI oscillator (factory calibrated) ACCHSI -1 1 % TA 25 °C 69
Accuracy of HSI oscillator (factory calibrated) ACCHSI -2 2 % VDD = 5 V, -25°C TA 85 °C 69
Accuracy of HSI oscillator (factory calibrated) ACCHSI -3 3 % 2.95 V VDD 5.5 V, -40°C TA 125 °C 69
HSI oscillator power consumption IDD(HSI) 170 250 µA 69
LSI frequency fLSI 110 128 150 kHz 71
ADC clock frequency fADC 1 4 MHz VDD= 2.95 to 5.5 V 85
ADC clock frequency fADC 1 6 MHz VDD= 4.5 to 5.5 V 85
Analog supply VDDA 3 5.5 V 85
Total unadjusted error /ET/ 1 2.5 LSB fADC = 2 MHz, VDDA = 5 V 86
SPI clock frequency fSCK 0 8 MHz Master mode 80
Supply current in Run mode, code executed from Flash IDD(RUN) 7 8 mA fCPU = fMASTER = 16 MHz, HSE user ext. clock (16 MHz), VDD = 5 V 57
Supply current in Run mode, code executed from Flash IDD(RUN) 7 8 mA fCPU = fMASTER = 16 MHz, HSE user ext. clock (16 MHz), VDD = 3.3 V 58
Supply current in wait mode IDD(WFI) 1.55 2 mA fCPU = fMASTER = 16 MHz, HSE user ext. clock (16 MHz), VDD = 5 V 58
Supply current in halt mode IDD(H) 6.5 25 µA Flash in power-down mode, HSI clock after wakeup, VDD = 5 V, Max at 85 °C 60

CAD (KiCad official)

  • Symbol: STM8S105C6T3
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm8s105c6t3-etched.step / stm8s105c6t3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s105c6t3.step / stm8s105c6t3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (121 pp, sha256 b1007bc27bb78327, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF