component
STM8S103F2M6
Public Made by Adomby adom
STMicroelectronics Microcontroller Units (MCUs/MPUs/SOCs), SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8S103F2M6
STMicroelectronics · Microcontroller Units (MCUs/MPUs/SOCs) · SOP-20-300mil
STM8S103F2M6 from STMicroelectronics, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD4/BEEP/TIM2_CH1/UART1_CK | bidirectional | Port D4 configurable as Timer 2 channel 1, BEEP output, or UART1 clock with high sink output capability. |
| 2 | PD5/AIN5/UART1_TX | bidirectional | Port D5 configurable as analog input 5 or UART1 transmit data with high sink output capability. |
| 3 | PD6/AIN6/UART1_RX | bidirectional | Port D6 configurable as analog input 6 or UART1 receive data with high sink output capability. |
| 4 | NRST | input | Active-low reset input with 30 to 80 kΩ internal pull-up resistor and approximately 75 ns input filter. |
| 5 | PA1/OSCIN | bidirectional | Port A1 configurable as crystal/oscillator input or standard GPIO with weak pull-up; O1 output speed. |
| 6 | PA2/OSCOUT | bidirectional | Port A2 configurable as crystal/oscillator output or standard GPIO; O1 output speed. |
| 7 | VSS | power_in | Digital ground; all ground pins must be connected to complete power distribution. |
| 8 | VCAP | passive | Internal voltage regulator bypass capacitor connection; requires 470 nF to 3.3 µF capacitor to ground with ESR 0.3 Ω and ESL 15 nH maximum. |
| 9 | VDD | power_in | Digital power supply; 2.95 to 5.5 V operating voltage range; all supply pins must be connected to external power. |
| 10 | PA3/TIM2_CH3/SPI_NSS | bidirectional | Port A3 configurable as Timer 2 channel 3, SPI master/slave select, or GPIO with high sink output capability and O3 speed. |
| 11 | PB5/I2C_SDA/TIM1_BKIN | bidirectional | Port B5 configurable as I2C data (true open-drain), Timer 1 break input, or GPIO; O1 output speed. |
| 12 | PB4/I2C_SCL | bidirectional | Port B4 configurable as I2C clock (true open-drain), ADC external trigger, or GPIO; O1 output speed. |
| 13 | PC3/TIM1_CH3/TLI | bidirectional | Port C3 configurable as Timer 1 channel 3, top-level interrupt, or GPIO with high sink output capability and O3 speed. |
| 14 | PC4/CLK_CCO/TIM1_CH4/AIN2 | bidirectional | Port C4 configurable as configurable clock output, Timer 1 channel 4, analog input 2, or GPIO with high sink output capability and O3 speed. |
| 15 | PC5/SPI_SCK | bidirectional | Port C5 configurable as SPI clock, Timer 2 channel 1, or GPIO with high sink output capability and O3 speed. |
| 16 | PC6/SPI_MOSI | bidirectional | Port C6 configurable as SPI master out/slave in, Timer 1 channel 1, or GPIO with high sink output capability and O3 speed. |
| 17 | PC7/SPI_MISO | bidirectional | Port C7 configurable as SPI master in/slave out, Timer 1 channel 2, or GPIO with high sink output capability and O3 speed. |
| 18 | PD1/SWIM | bidirectional | Port D1 configurable as SWIM data interface or GPIO with high sink output capability, O4 speed, and internal pull-up during reset phase. |
| 19 | PD2/AIN3 | bidirectional | Port D2 configurable as analog input 3, Timer 2 channel 3, or GPIO with high sink output capability and O3 speed. |
| 20 | PD3/AIN4/TIM2_CH2/ADC_ETR | bidirectional | Port D3 configurable as analog input 4, Timer 2 channel 2, ADC external trigger, or GPIO with high sink output capability and O3 speed. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOP-20-300mil |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
STM8S103F2M6 - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
stm8s103f2m6-etched.step/stm8s103f2m6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s103f2m6.step/stm8s103f2m6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (121 pp, sha256
ac23789ac0a2f408, retrieved 2026-10-01, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).