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STM8S005C6T6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs stm8s005c6t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
viewers stm8s005c6t6: viewers · Ray 12d ago
package.json Publish 0.1.0 · Ray 12d ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md Initial commit: component/stm8s005c6t6 · Ray 12d ago
stm8s005c6t6-etched.fit.json stm8s005c6t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
stm8s005c6t6-etched.glb stm8s005c6t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
stm8s005c6t6-etched.step stm8s005c6t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
stm8s005c6t6.glb Publish 0.1.0 · Ray 12d ago
stm8s005c6t6.kicad_mod Publish 0.1.0 · Ray 12d ago
stm8s005c6t6.kicad_sym Publish 0.1.0 · Ray 12d ago
stm8s005c6t6.lbr Publish 0.1.0 · Ray 12d ago
stm8s005c6t6.step Publish 0.1.0 · Ray 12d ago

STM8S005C6T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM8S005C6T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST input Active-low system reset input with internal 30-80 kΩ pull-up resistor; input low voltage VIL maximum 0.3×VDD.
2 PA1/OSCIN input Port A bit 1 or external crystal oscillator/clock input; Schmitt trigger input accepts 1-16 MHz, VIL/VIH per I/O specifications.
3 PA2/OSCOUT output Port A bit 2 or crystal oscillator output feedback pin for resonator drive circuit.
4 VSSIO_1 power_in I/O ground power supply pin; must be connected to external power supply ground.
5 VSS power_in Digital ground power supply pin; must be connected to external power supply ground.
6 VCAP passive Internal 1.8 V regulator output capacitor pin; requires 470-3300 nF external capacitor with 0.3 ohm ESR and 15 nH ESL.
7 VDD power_in Digital power supply pin; 2.95-5.5 V operating voltage range, must be connected to external power supply.
8 VDDIO_1 power_in I/O power supply pin; 2.95-5.5 V operating voltage range, must be connected to external power supply.
9 PA3/TIM2_CH3 bidirectional Port A bit 3, Timer 2 channel 3 output, or TIM3_CH1 (with AFR1 remap option).
10 PA4 bidirectional Port A bit 4 with high-sink output capability supporting 10-20 mA sink at 5 V; programmable speed (O3 default slow).
11 PA5 bidirectional Port A bit 5 with high-sink output capability supporting 10-20 mA sink at 5 V; programmable speed (O3 default slow).
12 PA6 bidirectional Port A bit 6 with high-sink output capability supporting 10-20 mA sink at 5 V; programmable speed (O3 default slow).
13 VDDA power_in Analog power supply pin; 2.95-5.5 V operating voltage range, should be separate from digital VDD with filtering.
14 VSSA power_in Analog ground power supply pin; must be connected to external power supply ground.
15 PB7/AIN7 bidirectional Port B bit 7 or analog input channel 7; 10-bit ADC input with 0 to VDDA conversion range.
16 PB6/AIN6 bidirectional Port B bit 6 or analog input channel 6; 10-bit ADC input with 0 to VDDA conversion range.
17 PB5/AIN5 bidirectional Port B bit 5, analog input channel 5, or I2C_SDA (with AFR6 remap); 10-bit ADC input with 0 to VDDA conversion range.
18 PB4/AIN4 bidirectional Port B bit 4, analog input channel 4, or I2C_SCL (with AFR6 remap); 10-bit ADC input with 0 to VDDA conversion range.
19 PB3/AIN3 bidirectional Port B bit 3, analog input channel 3, or TIM1_ETR (with AFR5 remap); 10-bit ADC input with 0 to VDDA conversion range.
20 PB2/AIN2 bidirectional Port B bit 2, analog input channel 2, or TIM1_CH3N (with AFR5 remap); 10-bit ADC input with 0 to VDDA conversion range.
21 PB1/AIN1 bidirectional Port B bit 1, analog input channel 1, or TIM1_CH2N (with AFR5 remap); 10-bit ADC input with 0 to VDDA conversion range.
22 PB0/AIN0 bidirectional Port B bit 0, analog input channel 0, or TIM1_CH1N (with AFR5 remap); 10-bit ADC input with 0 to VDDA conversion range.
23 PE7/AIN8 bidirectional Port E bit 7 or analog input channel 8; 10-bit ADC input with 0 to VDDA conversion range.
24 PE6/AIN9 bidirectional Port E bit 6 or analog input channel 9; 10-bit ADC input with 0 to VDDA conversion range.
25 PE5/SPI_NSS bidirectional Port E bit 5 or SPI master/slave select input pin; standard output type.
26 PC1/TIM1_CH1/UART2_CK bidirectional Port C bit 1, Timer 1 channel 1 output, or UART2 synchronous clock; high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
27 PC2/TIM1_CH2 bidirectional Port C bit 2 or Timer 1 channel 2 output; high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
28 PC3/TIM1_CH3 bidirectional Port C bit 3 or Timer 1 channel 3 output; high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
29 PC4/TIM1_CH4 bidirectional Port C bit 4 or Timer 1 channel 4 output; high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
30 PC5/SPI_SCK bidirectional Port C bit 5 or SPI clock output pin; high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow), maximum 8 Mbit/s.
31 VSSIO_2 power_in I/O ground power supply pin; must be connected to external power supply ground.
32 VDDIO_2 power_in I/O power supply pin; 2.95-5.5 V operating voltage range, must be connected to external power supply.
33 PC6/SPI_MOSI bidirectional Port C bit 6 or SPI master out/slave in data pin; high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow), maximum 8 Mbit/s.
34 PC7/SPI_MISO bidirectional Port C bit 7 or SPI master in/slave out data pin; high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow), maximum 8 Mbit/s.
35 PG0 bidirectional Port G bit 0; standard I/O pin with floating input and push-pull output.
36 PG1 bidirectional Port G bit 1; standard I/O pin with floating input and push-pull output.
37 PE3/TIM1_BKIN bidirectional Port E bit 3 or Timer 1 break input; break input forces timer complementary outputs into safe state.
38 PE2/I2C_SDA tri_state Port E bit 2 or I2C data line; true open-drain output without P-buffer or weak pull-up, requires external pull-up resistor for I2C bus operation.
39 PE1/I2C_SCL tri_state Port E bit 1 or I2C clock line; true open-drain output without P-buffer or weak pull-up, requires external pull-up resistor for I2C bus operation.
40 PE0/CLK_CCO bidirectional Port E bit 0, configurable clock output, or TIM1_BKIN (with AFR3 remap); high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
41 PD0/TIM3_CH2 bidirectional Port D bit 0, Timer 3 channel 2 output, TIM1_BKIN (with AFR3 remap), or CLK_CCO (with AFR2 remap); high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
42 PD1/SWIM bidirectional Port D bit 1 or SWIM single-wire interface data pin; input pull-up during reset, programmable speed (O4 default fast).
43 PD2/TIM3_CH1 bidirectional Port D bit 2, Timer 3 channel 1 output, or TIM2_CH3 (with AFR1 remap); high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
44 PD3/TIM2_CH2 bidirectional Port D bit 3, Timer 2 channel 2 output, or ADC external trigger input (with AFR0 remap); high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
45 PD4/TIM2_CH1 bidirectional Port D bit 4, Timer 2 channel 1 output, or BEEP output 1-4 kHz (with AFR7 remap); high-sink output (10-20 mA at 5 V), programmable speed (O3 default slow).
46 PD5/UART2_TX output Port D bit 5 or UART2 transmit data output; standard output type, up to 1 Mbit/s.
47 PD6/UART2_RX input Port D bit 6 or UART2 receive data input; Schmitt trigger input, up to 1 Mbit/s.
48 PD7/TLI input Port D bit 7, top-level interrupt external interrupt input, or TIM1_CH4 (with AFR4 remap); Schmitt trigger input.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: STM8S005C6T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm8s005c6t6-etched.step / stm8s005c6t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s005c6t6.step / stm8s005c6t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (97 pp, sha256 97b9faba420e5e3a, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF