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STM8L152R8T6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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STM8L152R8T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM8L152R8T6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0/USART1_CK/SWIM/BEEP/IR_TIM bidirectional Port A0. Default main function after reset is SWIM (Single Wire Interface Module) input/output plus Beep output and Infra-red Timer output; alternate functions include USART1 synchronous clock. High-sink capable I/O.
2 NRST/PA1 bidirectional Device reset input, active low, with internal pull-up. May be reconfigured as general purpose output PA1 (push-pull only) via option byte.
3 PA2/OSC_IN/[USART1_TX]/[SPI1_MISO] bidirectional Port A2, high-sink FT I/O. Alternate: HSE crystal oscillator input; optional remap to USART1_TX or SPI1_MISO.
4 PA3/OSC_OUT/[USART1_RX]/[SPI1_MOSI] bidirectional Port A3, high-sink FT I/O. Alternate: HSE crystal oscillator output; optional remap to USART1_RX or SPI1_MOSI.
5 PA4/TIM2_BKIN/[TIM2_ETR]/LCD_COM0/ADC1_IN2/[COMP1_INP] bidirectional Port A4, high-sink FT I/O. Default alternates: Timer 2 break input, LCD COM0, ADC1 input 2; optional TIM2 external trigger and comparator 1 positive input.
6 PA5/TIM3_BKIN/[TIM3_ETR]/LCD_COM1/ADC1_IN1/[COMP1_INP] bidirectional Port A5, high-sink FT I/O. Default alternates: Timer 3 break input, LCD COM1, ADC1 input 1; optional TIM3 external trigger and comparator 1 positive input.
7 PA6/ADC1_TRIG/LCD_COM2/ADC1_IN0/[COMP1_INP] bidirectional Port A6, high-sink FT I/O. ADC1 external trigger, LCD COM2, ADC1 input 0; optional comparator 1 positive input.
8 PA7/LCD_SEG0/TIM5_CH1 bidirectional Port A7, high-sink FT I/O. LCD segment 0, Timer 5 channel 1.
9 VSSA/VREF- power_in Analog ground reference and ADC1 negative voltage reference. Tie to system ground.
10 VSS1 power_in Digital I/O ground return.
11 VDD1 power_in Digital power supply, 1.65 V to 3.6 V (1.8 V to 3.6 V with BOR enabled).
12 VDDA power_in Analog supply voltage for ADC/DAC/comparators. Nominally tied to VDD via filter.
13 VREF+/VREF+_DAC power_in ADC1 and DAC1/2 positive voltage reference input. Must be between 2.4 V and VDDA.
14 PG0/LCD_SEG28/USART3_RX/[TIM2_BKIN] bidirectional Port G0, high-sink FT I/O. LCD segment 28, USART3 receive; optional TIM2 break input.
15 PG1/LCD_SEG29/USART3_TX/[TIM3_BKIN] bidirectional Port G1, high-sink FT I/O. LCD segment 29, USART3 transmit; optional TIM3 break input.
16 PG2/LCD_SEG30/USART3_CK bidirectional Port G2, high-sink FT I/O. LCD segment 30, USART3 synchronous clock.
17 PG3/LCD_SEG31/[TIM3_ETR] bidirectional Port G3, high-sink FT I/O. LCD segment 31; optional TIM3 external trigger.
18 Res. power_in Reserved pin. Must be tied to VDD.
19 PE0/LCD_SEG1/TIM5_CH2 bidirectional Port E0, high-sink FT I/O. LCD segment 1, Timer 5 channel 2.
20 PE1/TIM1_CH2N/LCD_SEG2 bidirectional Port E1, high-sink FT I/O. Timer 1 inverted channel 2, LCD segment 2.
21 PE2/TIM1_CH3N/LCD_SEG3/[CCO] bidirectional Port E2, high-sink FT I/O. Timer 1 inverted channel 3, LCD segment 3; optional configurable clock output.
22 PE3/LCD_SEG4/USART2_RX bidirectional Port E3, high-sink FT I/O. LCD segment 4, USART2 receive.
23 PE4/LCD_SEG5/DAC_TRIG2/USART2_TX bidirectional Port E4, high-sink FT I/O. LCD segment 5, DAC2 trigger, USART2 transmit.
24 PE5/LCD_SEG6/ADC1_IN23/[COMP1_INP]/[COMP2_INP]/USART2_CK bidirectional Port E5, high-sink FT I/O. LCD segment 6, ADC1 input 23, USART2 synchronous clock; optional comparator 1/2 positive input.
25 PD0/TIM3_CH2/[ADC1_TRIG]/LCD_SEG7/ADC1_IN22/[COMP2_INP] bidirectional Port D0, high-sink FT I/O. Timer 3 channel 2, LCD segment 7, ADC1 input 22; optional ADC1 trigger and comparator 2 positive input.
26 PD1/TIM3_ETR/LCD_COM3/ADC1_IN21/[COMP1_INP]/[COMP2_INP] bidirectional Port D1, high-sink FT I/O. Timer 3 external trigger, LCD COM3, ADC1 input 21; optional comparator 1/2 positive input.
27 PD2/TIM1_CH1/LCD_SEG8/ADC1_IN20/[COMP1_INP] bidirectional Port D2, high-sink FT I/O. Timer 1 channel 1, LCD segment 8, ADC1 input 20; optional comparator 1 positive input.
28 PD3/TIM1_ETR/LCD_SEG9/ADC1_IN19/[COMP1_INP] bidirectional Port D3, high-sink FT I/O. Timer 1 external trigger, LCD segment 9, ADC1 input 19; optional comparator 1 positive input.
29 VDD3 power_in I/O supply voltage, 1.65 V to 3.6 V.
30 VSS3 power_in I/O ground return.
31 PB0/TIM2_CH1/LCD_SEG10/ADC1_IN18/[COMP1_INP] bidirectional Port B0, high-sink FT I/O. Timer 2 channel 1, LCD segment 10, ADC1 input 18; optional comparator 1 positive input.
32 PB1/TIM3_CH1/LCD_SEG11/ADC1_IN17/[COMP1_INP] bidirectional Port B1, high-sink FT I/O. Timer 3 channel 1, LCD segment 11, ADC1 input 17; optional comparator 1 positive input.
33 PB2/TIM2_CH2/LCD_SEG12/ADC1_IN16/[COMP1_INP] bidirectional Port B2, high-sink FT I/O. Timer 2 channel 2, LCD segment 12, ADC1 input 16; optional comparator 1 positive input.
34 PB3/TIM2_ETR/LCD_SEG13/ADC1_IN15/[COMP1_INP] bidirectional Port B3, high-sink FT I/O. Timer 2 external trigger, LCD segment 13, ADC1 input 15; optional comparator 1 positive input.
35 PB4/SPI1_NSS/LCD_SEG14/ADC1_IN14/[COMP1_INP] bidirectional Port B4, high-sink FT I/O. SPI1 master/slave select, LCD segment 14, ADC1 input 14; optional comparator 1 positive input.
36 PB5/SPI1_SCK/LCD_SEG15/ADC1_IN13/[COMP1_INP] bidirectional Port B5, high-sink FT I/O. SPI1 clock, LCD segment 15, ADC1 input 13; optional comparator 1 positive input.
37 PB6/SPI1_MOSI/LCD_SEG16/ADC1_IN12/[COMP1_INP] bidirectional Port B6, high-sink FT I/O. SPI1 master out / slave in, LCD segment 16, ADC1 input 12; optional comparator 1 positive input.
38 PB7/SPI1_MISO/LCD_SEG17/ADC1_IN11/[COMP1_INP] bidirectional Port B7, high-sink FT I/O. SPI1 master in / slave out, LCD segment 17, ADC1 input 11; optional comparator 1 positive input.
39 PF0/ADC1_IN24/DAC_OUT1/[USART3_TX] bidirectional Port F0, high-sink FT I/O. ADC1 input 24, DAC channel 1 output; optional USART3 transmit remap.
40 PF1/ADC1_IN25/DAC_OUT2/[USART3_RX] bidirectional Port F1, high-sink FT I/O. ADC1 input 25, DAC channel 2 output; optional USART3 receive remap.
41 PF4/LCD_SEG36/[LCD_COM4] bidirectional Port F4, high-sink FT I/O. LCD segment 36; optional LCD COM4.
42 PF5/LCD_SEG37/[LCD_COM5] bidirectional Port F5, high-sink FT I/O. LCD segment 37; optional LCD COM5.
43 PF6/LCD_SEG38/[LCD_COM6] bidirectional Port F6, high-sink FT I/O. LCD segment 38; optional LCD COM6.
44 PF7/LCD_SEG39/[LCD_COM7] bidirectional Port F7, high-sink FT I/O. LCD segment 39; optional LCD COM7.
45 PD4/TIM1_CH2/LCD_SEG18/ADC1_IN10/[COMP1_INP] bidirectional Port D4, high-sink FT I/O. Timer 1 channel 2, LCD segment 18, ADC1 input 10; optional comparator 1 positive input.
46 PD5/TIM1_CH3/LCD_SEG19/ADC1_IN9/[COMP1_INP] bidirectional Port D5, high-sink FT I/O. Timer 1 channel 3, LCD segment 19, ADC1 input 9; optional comparator 1 positive input.
47 PD6/TIM1_BKIN/LCD_SEG20/ADC1_IN8/RTC_CALIB/[COMP1_INP]/VREFINT bidirectional Port D6, high-sink FT I/O. Timer 1 break input, LCD segment 20, ADC1 input 8, RTC calibration output, internal reference voltage output; optional comparator 1 positive input.
48 PD7/TIM1_CH1N/LCD_SEG21/ADC1_IN7/RTC_ALARM/[COMP1_INP]/VREFINT bidirectional Port D7, high-sink FT I/O. Timer 1 inverted channel 1, LCD segment 21, ADC1 input 7, RTC alarm output, internal reference voltage output; optional comparator 1 positive input.
49 PG4/LCD_SEG32/SPI2_NSS bidirectional Port G4, high-sink FT I/O. LCD segment 32, SPI2 master/slave select.
50 PG5/LCD_SEG33/SPI2_SCK bidirectional Port G5, high-sink FT I/O. LCD segment 33, SPI2 clock.
51 PG6/LCD_SEG34/SPI2_MOSI bidirectional Port G6, high-sink FT I/O. LCD segment 34, SPI2 master out / slave in.
52 PG7/LCD_SEG35/SPI2_MISO bidirectional Port G7, high-sink FT I/O. LCD segment 35, SPI2 master in / slave out.
53 PC0/I2C1_SDA bidirectional Port C0, true open-drain FT I/O. I2C1 data line.
54 PC1/I2C1_SCL bidirectional Port C1, true open-drain FT I/O. I2C1 clock line.
55 VDD2 power_in I/O supply voltage, 1.65 V to 3.6 V.
56 VSS2 power_in I/O ground return.
57 PC2/USART1_RX/LCD_SEG22/ADC1_IN6/[COMP1_INP]/VREFINT bidirectional Port C2, high-sink FT I/O. USART1 receive, LCD segment 22, ADC1 input 6, internal reference voltage output; optional comparator 1 positive input.
58 PC3/USART1_TX/LCD_SEG23/ADC1_IN5/[COMP2_INM]/[COMP1_INP] bidirectional Port C3, high-sink FT I/O. USART1 transmit, LCD segment 23, ADC1 input 5; optional comparator 2 negative input or comparator 1 positive input.
59 PC4/USART1_CK/I2C1_SMB/[CCO]/LCD_SEG24/ADC1_IN4/[COMP2_INM]/[COMP1_INP] bidirectional Port C4, high-sink FT I/O. USART1 synchronous clock, I2C1 SMBus alert, LCD segment 24, ADC1 input 4; optional CCO, comparator 2 negative or comparator 1 positive input.
60 PC5/OSC32_IN/[SPI1_NSS]/[USART1_TX] bidirectional Port C5, high-sink FT I/O. LSE oscillator input; optional SPI1 master/slave select or USART1 transmit remap.
61 PC6/OSC32_OUT/[SPI1_SCK]/[USART1_RX] bidirectional Port C6, high-sink FT I/O. LSE oscillator output; optional SPI1 clock or USART1 receive remap.
62 PC7/LCD_SEG25/ADC1_IN3/[COMP2_INM]/[COMP1_INP] bidirectional Port C7, high-sink FT I/O. LCD segment 25, ADC1 input 3; optional comparator 2 negative or comparator 1 positive input.
63 PE6/LCD_SEG26/PVD_IN/TIM5_BKIN bidirectional Port E6, high-sink FT I/O. LCD segment 26, Programmable Voltage Detector input, Timer 5 break input.
64 PE7/LED_SEG27/TIM5_ETR bidirectional Port E7, high-sink FT I/O. LCD segment 27, Timer 5 external trigger.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category MCU
Pins 64

Ordering variants

Same part, different packaging or reel option.

  • STM8L152R8T6R6T6
  • STM8L152R8T6
  • STM8L152R8T6M8T6
  • STM8L152R8T6C8T6
  • STM8L152R8T6C8U6

CAD (KiCad official)

  • Symbol: STM8L152R8T6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm8l152r8t6-etched.step / stm8l152r8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8l152r8t6.step / stm8l152r8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (134 pp, sha256 6ec62e0638c0bbbb, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF