# STM8L151R6T6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM8L151R6T6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA0 | bidirectional | Port A0 with SWIM input/output, BEEP and IR timer output; input pull-up during reset and after reset release, high sink LED driver capability. |
| 2 | NRST/PA1 | bidirectional | Reset input with pull-up at power-up; as general purpose pin it can be configured only as output push-pull (PA1). |
| 3 | PA2 | bidirectional | Port A2 with HSE oscillator input, USART1 transmit and SPI1 MISO alternate functions; high sink/source capability (20 mA). |
| 4 | PA3 | bidirectional | Port A3 with HSE oscillator output, USART1 receive and SPI1 MOSI alternate functions; high sink/source capability (20 mA). |
| 5 | PA4 | bidirectional | Port A4 with TIM2 break input, ADC1 input 2 and comparator 1 positive input; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 6 | PA5 | bidirectional | Port A5 with TIM3 break input, ADC1 input 1 and comparator 1 positive input; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 7 | PA6 | bidirectional | Port A6 with ADC1 trigger, ADC1 input 0 and comparator 1 positive input; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 8 | PA7 | bidirectional | Port A7 with TIM5 channel 1 alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 9 | VSSA/VREF- | power_in | Analog ground voltage and ADC1 negative voltage reference. |
| 10 | VSS1 | power_in | I/O ground; must not be left unconnected. |
| 11 | VDD1 | power_in | Digital power supply 1.65 to 3.6 V for I/Os and internal regulator; must not be left unconnected. |
| 12 | VDDA | power_in | Analog supply voltage 1.65 to 3.6 V, minimum 1.8 V when ADC1 is used; must be connected to VDD. |
| 13 | VREF+ | power_in | ADC1 and DAC1/2 positive voltage reference, provided externally. |
| 14 | PG0 | bidirectional | Port G0 with USART3 receive and TIM2 break input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 15 | PG1 | bidirectional | Port G1 with USART3 transmit and TIM3 break input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 16 | PG2 | bidirectional | Port G2 with USART3 synchronous clock alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 17 | PG3 | bidirectional | Port G3 with TIM3 trigger alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 18 | Res. | passive | Reserved on STM8L151 devices and must be tied to VDD. |
| 19 | PE0 | bidirectional | Port E0 with TIM5 channel 2 alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 20 | PE1 | bidirectional | Port E1 with TIM1 inverted channel 2 alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 21 | PE2 | bidirectional | Port E2 with TIM1 inverted channel 3 and configurable clock output alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 22 | PE3 | bidirectional | Port E3 with USART2 receive alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 23 | PE4 | bidirectional | Port E4 with DAC trigger 2 and USART2 transmit alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 24 | PE5 | bidirectional | Port E5 with ADC1 input 23, comparator positive inputs and USART2 synchronous clock alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 25 | PD0 | bidirectional | Port D0 with TIM3 channel 2, ADC1 input 22 and comparator 2 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 26 | PD1 | bidirectional | Port D1 with TIM3 trigger, ADC1 input 21 and comparator positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 27 | PD2 | bidirectional | Port D2 with TIM1 channel 1, ADC1 input 20 and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 28 | PD3 | bidirectional | Port D3 with TIM1 trigger, ADC1 input 19 and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 29 | VDD3 | power_in | I/O supply voltage; must not be left unconnected. |
| 30 | VSS3 | power_in | I/O ground voltage; must not be left unconnected. |
| 31 | PB0 | bidirectional | Port B0 with TIM2 channel 1, ADC1 input 18 and comparator 1 positive input alternate functions; pull-up applied during reset phase. |
| 32 | PB1 | bidirectional | Port B1 with TIM3 channel 1, ADC1 input 17 and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 33 | PB2 | bidirectional | Port B2 with TIM2 channel 2, ADC1 input 16 and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 34 | PB3 | bidirectional | Port B3 with TIM2 trigger, ADC1 input 15 and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 35 | PB4 | bidirectional | Port B4 with SPI1 NSS, ADC1 input 14, DAC channel 2 output and comparator 1 positive input alternate functions; pull-up applied during reset phase. |
| 36 | PB5 | bidirectional | Port B5 with SPI1 clock, ADC1 input 13, DAC channel 2 output and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 37 | PB6 | bidirectional | Port B6 with SPI1 MOSI, ADC1 input 12, DAC channel 2 output and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 38 | PB7 | bidirectional | Port B7 with SPI1 MISO, ADC1 input 11 and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 39 | PF0 | bidirectional | Port F0 with ADC1 input 24, DAC 1 output and USART3 transmit alternate functions; high sink/source capability (20 mA). |
| 40 | PF1 | bidirectional | Port F1 with ADC1 input 25, DAC channel 2 output and USART3 receive alternate functions; high sink/source capability (20 mA). |
| 41 | PF4 | bidirectional | Port F4 with LCD segment 36 and LCD_COM4 alternate functions as listed for the 64-pin package; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 42 | PF5 | bidirectional | Port F5 with LCD segment 37 and LCD_COM5 alternate functions as listed for the 64-pin package; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 43 | PF6 | bidirectional | Port F6 with LCD segment 38 and LCD_COM6 alternate functions as listed for the 64-pin package; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 44 | PF7 | bidirectional | Port F7 with LCD segment 39 and LCD_COM7 alternate functions as listed for the 64-pin package; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 45 | PD4 | bidirectional | Port D4 with TIM1 channel 2, ADC1 input 10, SPI2 MISO and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 46 | PD5 | bidirectional | Port D5 with TIM1 channel 3, ADC1 input 9, SPI2 MOSI and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 47 | PD6 | bidirectional | Port D6 with TIM1 break input, ADC1 input 8, RTC calibration, SPI2 clock and internal reference voltage output alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 48 | PD7 | bidirectional | Port D7 with TIM1 inverted channel 1, ADC1 input 7, RTC alarm, SPI2 NSS and internal reference voltage output alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 49 | PG4 | bidirectional | Port G4 with SPI2 NSS alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 50 | PG5 | bidirectional | Port G5 with SPI2 clock alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 51 | PG6 | bidirectional | Port G6 with SPI2 MOSI alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 52 | PG7 | bidirectional | Port G7 with SPI2 MISO alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 53 | PC0 | bidirectional | Port C0 with I2C1 SDA alternate function; true open-drain I/O. |
| 54 | PC1 | bidirectional | Port C1 with I2C1 SCL alternate function; true open-drain I/O. |
| 55 | VDD2 | power_in | I/O supply voltage; must not be left unconnected. |
| 56 | VSS2 | power_in | I/O ground voltage; must not be left unconnected. |
| 57 | PC2 | bidirectional | Port C2 with USART1 receive, ADC1 input 6, comparator 1 positive input and internal reference voltage output alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 58 | PC3 | bidirectional | Port C3 with USART1 transmit, ADC1 input 5, comparator 2 negative input and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 59 | PC4 | bidirectional | Port C4 with USART1 synchronous clock, I2C1 SMBus, configurable clock output, ADC1 input 4 and comparator alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 60 | PC5 | bidirectional | Port C5 with LSE oscillator input, SPI1 NSS and USART1 transmit alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 61 | PC6 | bidirectional | Port C6 with LSE oscillator output, SPI1 clock and USART1 receive alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 62 | PC7 | bidirectional | Port C7 with ADC1 input 3, USART3 synchronous clock, comparator 2 negative input and comparator 1 positive input alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 63 | PE6 | bidirectional | Port E6 with PVD input, TIM5 break input and USART3 transmit alternate functions; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |
| 64 | PE7 | bidirectional | Port E7 with TIM5 trigger, USART3 receive alternate function; FT (five-volt tolerant) I/O, high sink/source capability (20 mA). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD-VSS (including VDDA) | VDD-VSS | -0.3 |  | 4 | V | External supply voltage (including VDDA) | 69 |
| Input voltage on any other pin | VIN |  |  | 4 | V | Printed minimum is VSS-0.3 V, not numeric here | 69 |
| Total current into VDD power line (source) | IVDD |  |  | 80 | mA |  | 70 |
| Total current out of VSS ground line (sink) | IVSS |  |  | 80 | mA |  | 70 |
| Output current sunk by any other I/O and control pin | IIO |  |  | 25 | mA |  | 70 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 70 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 70 |
| System clock frequency | fSYSCLK | 0 |  | 16 | MHz | 1.65 V ≤ VDD < 3.6 V | 71 |
| Standard operating voltage | VDD | 1.8 |  | 3.6 | V | BOR detector enabled | 71 |
| Analog operating voltage | VDDA | 1.65 |  | 3.6 | V | ADC and DAC not used; must be at the same potential as VDD | 71 |
| Analog operating voltage (ADC or DAC used) | VDDA | 1.8 |  | 3.6 | V | ADC or DAC used | 71 |
| Power dissipation | PD |  |  | 416 | mW | TA = 85 °C, LQFP64, suffix 6 devices | 71 |
| Temperature range | TA | -40 |  | 85 | °C | 1.65 V ≤ VDD < 3.6 V (6 suffix version) | 71 |
| Junction temperature range | TJ | -40 |  | 105 | °C | -40 °C ≤ TA < 85 °C (6 suffix version) | 71 |
| Power-on reset threshold | VPOR | 1.3 | 1.5 | 1.65 | V | Rising edge | 72 |
| Power-down reset threshold | VPDR | 1.3 | 1.5 | 1.65 | V | Falling edge | 72 |
| Brown-out reset threshold 0 (falling edge) | VBOR0 | 1.67 | 1.7 | 1.74 | V | BOR_TH[2:0]=000, falling edge | 72 |
| Brown-out reset threshold 0 (rising edge) | VBOR0 | 1.69 | 1.75 | 1.8 | V | BOR_TH[2:0]=000, rising edge | 72 |
| Brown-out reset threshold 1 (falling edge) | VBOR1 | 1.87 | 1.93 | 1.97 | V | BOR_TH[2:0]=001, falling edge | 72 |
| Brown-out reset threshold 1 (rising edge) | VBOR1 | 1.96 | 2.04 | 2.07 | V | BOR_TH[2:0]=001, rising edge | 72 |
| Supply current in Run mode, code from RAM | IDD(RUN) |  | 1.62 | 1.79 | mA | HSI RC osc. 16 MHz, fCPU=16 MHz, all peripherals OFF, 85 °C (suffix 6) | 75 |
| Supply current in Run mode, code from Flash | IDD(RUN) |  | 3.54 | 3.67 | mA | HSI RC osc., fCPU=16 MHz, all peripherals OFF, 85 °C (suffix 6) | 76 |
| HSI accuracy (factory calibrated) | ACCHSI | -1 |  | 1 | % | VDD = 3.0 V, TA = 25 °C | 93 |
| HSI accuracy (factory calibrated) | ACCHSI | -1.5 |  | 1.5 | % | VDD = 3.0 V, 0 °C ≤ TA ≤ 55 °C | 93 |
| HSI accuracy (factory calibrated) | ACCHSI | -2 |  | 2 | % | VDD = 3.0 V, -10 °C ≤ TA ≤ 70 °C | 93 |
| HSI accuracy (factory calibrated) | ACCHSI | -2.5 |  | 2 | % | VDD = 3.0 V, -10 °C ≤ TA ≤ 85 °C | 93 |
| HSI accuracy (factory calibrated) | ACCHSI | -4.5 |  | 2 | % | VDD = 3.0 V, -10 °C ≤ TA ≤ 125 °C | 93 |
| HSI accuracy (factory calibrated) | ACCHSI | -4.5 |  | 3 | % | 1.65 V ≤ VDD ≤ 3.6 V, -40 °C ≤ TA ≤ 125 °C | 93 |
| HSI oscillator setup time (wakeup time) | tsu(HSI) |  | 3.7 | 6 | µs |  | 93 |
| HSI oscillator power consumption | IDD(HSI) |  | 100 | 140 | µA |  | 93 |
| LSI oscillator frequency | fLSI | 26 | 38 | 56 | kHz | VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C | 94 |
| RAM data retention voltage (Halt mode or Reset) | VRM | 1.65 |  |  | V | Halt mode (or Reset) | 95 |
| Flash operating voltage (all modes, read/write/erase) | VDD | 1.65 |  | 3.6 | V | fSYSCLK = 16 MHz | 96 |
| Programming time for 1 or 128 bytes (block) erase/write | tprog |  |  | 6 | ms | Cycles on programmed byte | 96 |
| Programming time for 1 to 128 bytes (block) write | tprog |  |  | 3 | ms | Cycles on erased byte | 96 |
| Erase/write cycles (program memory) | NRW | 10 |  |  | kcycles | TA = -40 to +85 °C (6 suffix) | 96 |
| Erase/write cycles (data memory) | NRW | 300 |  |  | kcycles | Data memory | 96 |
| Input leakage current, standard I/Os | Ilkg |  |  | 50 | nA | VSS ≤ VIN ≤ VDD | 98 |
| Input leakage current, true open drain I/Os | Ilkg |  |  | 200 | nA | VSS ≤ VIN ≤ VDD | 98 |
| Weak pull-up equivalent resistor | RPU | 30 | 45 | 60 | kΩ | VIN = VSS | 98 |
| I/O pin capacitance | CIO |  |  | 5 | pF |  | 98 |
| Output low level voltage for an I/O pin | VOL |  |  | 0.45 | V | IIO = +2 mA, VDD = 3.0 V | 101 |
| Output low level voltage for an I/O pin | VOL |  |  | 0.7 | V | IIO = +10 mA, VDD = 3.0 V | 101 |
| Output low level voltage, true open drain port | VOL |  |  | 0.45 | V | IIO = +3 mA, VDD = 3.0 V | 101 |
| NRST input high level voltage | VIH(NRST) | 1.4 |  |  | V |  | 103 |
| NRST input low level voltage | VIL(NRST) |  |  | 0.8 | V |  | 103 |
| NRST output low level voltage | VOL(NRST) |  |  | 0.4 | V | IOL = 2 mA, 2.7 V ≤ VDD ≤ 3.6 V | 103 |
| NRST pull-up equivalent resistor | RPU(NRST) | 30 | 45 | 60 | kΩ |  | 103 |
| NRST input filtered pulse | VF(NRST) |  |  | 50 | ns |  | 103 |
| Internal reference voltage output | VREFINT | 1.202 | 1.224 | 1.242 | V | Tested at VDD = 3 V ±10 mV | 111 |
| Stability of VREFINT over temperature | STABVREFINT |  | 20 | 50 | ppm/°C | -40 °C ≤ TA ≤ 125 °C | 111 |
| SPI1 clock frequency, master mode | fSCK | 0 |  | 8 | MHz | Master mode | 105 |
| SPI1 NSS hold time, slave mode | th(NSS) | 80 |  |  | ns | Slave mode | 105 |
| DAC settling time (full scale) | tsettling |  | 7 | 12 | µs | RL ≥ 5 kΩ, CL ≤ 50 pF | 114 |
| Input leakage current, PA0 with high sink LED driver | Ilkg |  |  | 200 | nA | PA0 with high sink LED driver capability | 98 |
| HSI oscillator frequency | fHSI |  | 16 |  | MHz | VDD = 3.0 V | 93 |
| LSE oscillator frequency | fLSE |  | 32.768 |  | kHz |  | 92 |
| Programming/erasing consumption | Iprog |  | 0.7 |  | mA | TA = +25 °C, VDD = 3.0 V | 96 |

## CAD (KiCad official)

- Symbol: `STM8L151R6T6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm8l151r6t6-etched.step` / `stm8l151r6t6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8l151r6t6.step` / `stm8l151r6t6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm8l151r6t6.pdf) (147 pp, sha256 `193f2133f3d81d2b`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm8l151r6t6-datasheet.pdf)