# STM8L151F2P6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · TSSOP-20

STM8L151F2P6 from STMicroelectronics, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC5/OSC32_IN | bidirectional | Port C5 is a high-sink I/O that also serves as the LSE oscillator input, with alternates SPI1_NSS, USART_TX and TIM2_CH1 (20-pin packages only). |
| 2 | PC6/OSC32_OUT | bidirectional | Port C6 is a high-sink I/O that also serves as the LSE oscillator output, with alternates SPI_SCK, USART_RX and TIM2_CH2 (20-pin packages only). |
| 3 | PA0 | bidirectional | Port A0 is the high-sink LED driver capable pin, input pull-up during reset and after reset release, with alternates USART_CK, SWIM input/output, BEEP output and infrared timer output. |
| 4 | NRST/PA1 | bidirectional | This pin is the reset input with pull-up at power-up (NRST), with an RPU of 30 to 60 kΩ and an input low level VIL(NRST) max of 0.8 V; as PA1 it can only be configured as output open-drain or push-pull. |
| 5 | PA2 | bidirectional | Port A2 is a high-sink I/O that also serves as the HSE oscillator input, with alternates USART_TX and SPI_MISO. |
| 6 | PA3 | bidirectional | Port A3 is a high-sink I/O that also serves as the HSE oscillator output, with alternates USART_RX and SPI_MOSI. |
| 7 | VSS | power_in | Ground voltage, also used as ADC1 negative voltage reference and analog ground (VSS / VREF- / VSSA). |
| 8 | VDD | power_in | Digital supply voltage, also used as ADC1 positive voltage reference (VDD / VDDA / VREF+), with a 1.65 to 3.6 V operating supply range. |
| 9 | PD0 | bidirectional | Port D0 is a high-sink I/O that also provides Timer 3 channel 2, ADC1_TRIG, ADC1 input 22 and comparator positive inputs. |
| 10 | PB0 | bidirectional | Port B0 is a high-sink I/O with a pull-up applied during reset, which is then input floating after reset release, and provides Timer 2 channel 1 and ADC1 input 18. |
| 11 | PB1 | bidirectional | Port B1 is a high-sink I/O that also provides Timer 3 channel 1, ADC1 input 17 and comparator 1 positive input. |
| 12 | PB2 | bidirectional | Port B2 is a high-sink I/O that also provides Timer 2 channel 2, ADC1 input 16 and comparator 1 positive input. |
| 13 | PB3 | bidirectional | Port B3 is a high-sink I/O that also provides Timer 2 external trigger, ADC1 input 15, RTC alarm and comparator 1 positive input. |
| 14 | PB4 | bidirectional | Port B4 is a high-sink I/O with a pull-up applied during reset, which is then input floating after reset release, and provides SPI1 master/slave select, ADC1 input 14 and comparator 1 positive input. |
| 15 | PB5 | bidirectional | Port B5 is a high-sink I/O that also provides SPI clock, ADC1 input 13 and comparator 1 positive input. |
| 16 | PB6 | bidirectional | Port B6 is a high-sink I/O that also provides SPI1 master out/slave in, ADC1 input 12 and comparator 1 positive input. |
| 17 | PB7 | bidirectional | Port B7 is a high-sink I/O that also provides SPI1 master in/slave out, ADC1 input 11 and comparator 1 positive input. |
| 18 | PC0 | bidirectional | Port C0 is a 5 V tolerant (FT) I/O with true open-drain capability that also serves as the I2C data line (I2C_SDA). |
| 19 | PC1 | bidirectional | Port C1 is a 5 V tolerant (FT) I/O with true open-drain capability that also serves as the I2C clock line (I2C_SCL). |
| 20 | PC4 | bidirectional | Port C4 is a high-sink I/O that also provides USART synchronous clock, I2C1_SMB, configurable clock output (CCO), ADC1 input 4 and comparator inputs. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External supply voltage (VDD, VDDA, VDDIO) VDD-VSS | VDD-VSS | -0.3 |  | 4 | V |  | 54 |
| Total current into VDD power line (source) | IVDD |  |  | 80 | mA |  | 56 |
| Total current out of VSS ground line (sink) | IVSS |  |  | 80 | mA |  | 56 |
| Output current sunk by any other I/O and control pin | IIO |  |  | 25 | mA |  | 56 |
| Output current sourced by any I/Os and control pin | IIO |  |  | -25 | mA |  | 56 |
| Injected current on any other pin | IINJ(PIN) | -5 |  | 5 | mA |  | 56 |
| Total injected current (sum of all I/O and control pins) | ΣIINJ(PIN) | -25 |  | 25 | mA |  | 56 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 56 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 56 |
| System clock frequency | fSYSCLK | 0 |  | 16 | MHz | 1.65 V ≤ VDD < 3.6 V | 57 |
| Standard operating voltage | VDD | 1.65 |  | 3.6 | V | Without BOR (1.8 V at power-up) | 57 |
| Analog operating voltage | VDDA | 1.65 |  | 3.6 | V | ADC1 not used; must be at same potential as VDD | 57 |
| Analog operating voltage | VDDA | 1.8 |  | 3.6 | V | ADC1 used | 57 |
| Temperature range | TA | -40 |  | 85 | °C | 6 suffix version, 1.65 V ≤ VDD < 3.6 V | 57 |
| Junction temperature range | TJ | -40 |  | 105 | °C | -40 °C ≤ TA < 85 °C, 6 suffix version | 57 |
| Power dissipation (TSSOP20) | PD |  |  | 181 | mW | TA = 85 °C, 6 suffix | 57 |
| Power-down reset threshold | VPDR | 1.3 | 1.5 | 1.65 | V | Falling edge | 58 |
| Brown-out reset threshold 0 (falling edge) | VBOR0 | 1.66 | 1.7 | 1.74 | V | Falling edge, BOR_TH[2:0]=000 | 58 |
| Brown-out reset threshold 0 (rising edge) | VBOR0 | 1.69 | 1.75 | 1.81 | V | Rising edge, BOR_TH[2:0]=000 | 58 |
| Supply current in Run mode (code from RAM, HSI) | IDD(RUN) |  | 0.39 | 0.49 | mA | All peripherals OFF, fCPU = 125 kHz, max at 85 °C | 60 |
| Supply current in Run mode (code from RAM, HSI) | IDD(RUN) |  | 1.85 | 2.12 | mA | All peripherals OFF, fCPU = 16 MHz, max at 85 °C | 60 |
| Supply current in Run mode (code from Flash, HSI) | IDD(RUN) |  | 0.43 | 0.56 | mA | All peripherals OFF, fCPU = 125 kHz, max at 85 °C | 60 |
| Supply current in Run mode (code from Flash, HSI) | IDD(RUN) |  | 3.8 | 4.75 | mA | All peripherals OFF, fCPU = 16 MHz, max at 85 °C | 60 |
| Accuracy of HSI oscillator (factory calibrated) | ACCHSI | -1.5 |  | 1.5 | % | VDD = 3.0 V, 0 °C ≤ TA ≤ 55 °C | 75 |
| Accuracy of HSI oscillator (factory calibrated) | ACCHSI | -2.5 |  | 2 | % | VDD = 3.0 V, -10 °C ≤ TA ≤ 85 °C | 75 |
| LSI oscillator frequency | fLSI | 26 | 38 | 56 | kHz | VDD = 1.65 V to 3.6 V | 76 |
| LSI oscillator wakeup time | tsu(LSI) |  |  | 200 | µs |  | 76 |
| LSI oscillator frequency drift | IDD(LSI) | -12 |  | 11 | % | 0 °C ≤ TA ≤ 85 °C | 76 |
| Operating voltage (all modes, read/write/erase) | VDD | 1.65 |  | 3.6 | V | fSYSCLK = 16 MHz | 78 |
| Programming time for 1 or 64 bytes (block) erase/write cycles | tprog |  |  | 6 | ms | On programmed byte | 78 |
| Programming time for 1 to 64 bytes (block) write cycles | tprog |  |  | 3 | ms | On erased byte | 78 |
| Data retention (program memory) after 10000 erase/write cycles | tRET | 30 |  |  | years | TA = -40 to +85 °C, TRET = +85 °C (3 and 6 suffix) | 78 |
| Erase/write cycles (program memory) | NRW | 10 |  |  | kcycles | TA = -40 to +85 °C (3 and 6 suffix) | 78 |
| Minimum supply voltage without losing RAM data | VRM | 1.65 |  |  | V | Halt mode (or Reset) | 78 |
| Input leakage current, high sink I/Os | Ilkg |  |  | 50 | nA | VSS ≤ VIN ≤ VDD | 80 |
| Input leakage current, true open drain I/Os | Ilkg |  |  | 200 | nA | VSS ≤ VIN ≤ VDD | 80 |
| Weak pull-up equivalent resistor | RPU | 30 | 45 | 60 | kΩ | VIN = VSS | 80 |
| Output low level voltage for an I/O pin (high sink) | VOL |  |  | 0.45 | V | IIO = +2 mA, VDD = 3.0 V | 83 |
| Output low level voltage for an I/O pin (high sink) | VOL |  |  | 0.7 | V | IIO = +10 mA, VDD = 3.0 V | 83 |
| Output low level voltage for an I/O pin (true open drain) | VOL |  |  | 0.45 | V | IIO = +3 mA, VDD = 3.0 V | 83 |
| Output low level voltage for PA0 with high sink LED driver | VOL |  |  | 0.45 | V | IIO = +20 mA, VDD = 2.0 V | 83 |
| NRST input low level voltage | VIL(NRST) |  |  | 0.8 | V |  | 85 |
| NRST input high level voltage | VIH(NRST) | 1.4 |  |  | V |  | 85 |
| NRST output low level voltage | VOL(NRST) |  |  | 0.4 | V | IOL = 2 mA, 2.7 V ≤ VDD ≤ 3.6 V | 85 |
| NRST pull-up equivalent resistor | RPU(NRST) | 30 | 45 | 60 | kΩ |  | 85 |
| Reference voltage output (VREFINT) | VREFINT out | 1.202 | 1.224 | 1.242 | V |  | 92 |
| Stability of VREFINT over temperature | STABVREFINT |  | 20 | 50 | ppm/°C | -40 °C ≤ TA ≤ 125 °C | 92 |
| ADC1 sampling clock frequency | fADC1 | 0.32 |  | 16 | MHz | 2.4 V ≤ VDDA ≤ 3.6 V, without zooming | 95 |
| Wakeup time from OFF state (ADC1) | tWKUP |  |  | 3 | µs |  | 95 |
| Comparator 1 startup time | tSTART |  | 7 | 10 | µs |  | 93 |
| Comparator 1 offset error | Voffset | -10 | 3 | 10 | mV |  | 93 |
| Comparator 1 current consumption | ICOMP1 |  | 160 | 260 | nA | Comparator consumption only | 93 |
| SPI1 clock frequency (master mode) | fSCK | 0 |  | 8 | MHz | Master mode | 87 |
| SPI1 clock rise and fall time | tr(SCK), tf(SCK) |  |  | 30 | ns | Capacitive load C = 30 pF | 87 |
| NSS hold time | th(NSS) | 80 |  |  | ns | Slave mode | 87 |
| Data input setup time | tsu(MI) | 30 |  |  | ns | Master mode | 87 |
| Data output valid time | tv(SO) |  |  | 60 | ns | Slave mode (after enable edge) | 87 |
| Thermal resistance junction-ambient TSSOP20 | ΘJA |  | 110 |  | °C/W | JEDEC JESD51-2, 4-layer PCB, natural convection | 118 |

## CAD (KiCad official)

- Symbol: `STM8L151F2P6`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `stm8l151f2p6-etched.step` / `stm8l151f2p6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8l151f2p6.step` / `stm8l151f2p6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm8l151f2p6.pdf) (123 pp, sha256 `56a41f554888e763`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm8l151f2p6-datasheet.pdf)