component

STM8L052R8T6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm8l052r8t6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs stm8l052r8t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
viewers stm8l052r8t6: viewers · Ray 13d ago
package.json Publish 0.1.0 · Ray 13d ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md Initial commit: component/stm8l052r8t6 · Ray 13d ago
stm8l052r8t6-etched.fit.json stm8l052r8t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
stm8l052r8t6-etched.glb stm8l052r8t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
stm8l052r8t6-etched.step stm8l052r8t6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
stm8l052r8t6.glb Publish 0.1.0 · Ray 13d ago
stm8l052r8t6.kicad_mod Publish 0.1.0 · Ray 13d ago
stm8l052r8t6.kicad_sym Publish 0.1.0 · Ray 13d ago
stm8l052r8t6.lbr Publish 0.1.0 · Ray 13d ago
stm8l052r8t6.step Publish 0.1.0 · Ray 13d ago

STM8L052R8T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM8L052R8T6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional Port A0 configurable as general purpose I/O, SWIM debug interface, beep output, or infrared timer output; high sink LED driver capability.
2 NRST/PA1 bidirectional Power-on reset input or configurable as Port A1 general purpose output only with push-pull or open-drain configuration; external interrupt source.
3 PA2 bidirectional Port A2 configurable as general purpose I/O, HSE oscillator input, alternate USART1 transmit, or alternate SPI1 MISO; 5V tolerant.
4 PA3 bidirectional Port A3 configurable as general purpose I/O, HSE oscillator output, alternate USART1 receive, or alternate SPI1 MOSI; 5V tolerant.
5 PA4 bidirectional Port A4 configurable as general purpose I/O, Timer 2 break input, alternate Timer 2 trigger, LCD common 0, or ADC1 input channel 2; 5V tolerant.
6 PA5 bidirectional Port A5 configurable as general purpose I/O, Timer 3 break input, alternate Timer 3 trigger, LCD common 1, or ADC1 input channel 1; 5V tolerant.
7 PA6 bidirectional Port A6 configurable as general purpose I/O, alternate ADC1 trigger, LCD common 2, or ADC1 input channel 0; 5V tolerant.
8 PA7 bidirectional Port A7 configurable as general purpose I/O, LCD segment 0, or Timer 5 channel 1; 5V tolerant.
9 VSSA/VREF- power_in Analog ground voltage and ADC1 negative voltage reference; must be connected to VSS; supply range 1.8 to 3.6 V.
10 VSS1 power_in I/O and digital power supply ground return; must not be left unconnected; supply range 1.8 to 3.6 V.
11 VDD1 power_in Digital power supply voltage for I/Os and internal regulator; must not be left unconnected; supply range 1.8 to 3.6 V.
12 VDDA power_in Analog supply voltage for ADC peripherals; must be connected to VDD; supply range 1.8 to 3.6 V.
13 VREF+ power_in ADC1 positive voltage reference; must be provided externally; supply range 1.8 to 3.6 V.
14 PG0 bidirectional Port G0 configurable as general purpose I/O, USART3 receive, or alternate Timer 2 break input; 5V tolerant.
15 PG1 bidirectional Port G1 configurable as general purpose I/O, USART3 transmit, or alternate Timer 3 break input; 5V tolerant.
16 PG2 bidirectional Port G2 configurable as general purpose I/O or USART3 synchronous clock; 5V tolerant.
17 PG3 bidirectional Port G3 configurable as general purpose I/O or alternate Timer 3 external trigger; 5V tolerant.
18 VLCD power_in LCD booster external capacitor connection for internal step-up converter to guarantee contrast control; supply range 1.8 to 3.6 V.
19 PE0 bidirectional Port E0 configurable as general purpose I/O, LCD segment 1, Timer 5 channel 2, or RTC tamper 1 detection input; 5V tolerant.
20 PE1 bidirectional Port E1 configurable as general purpose I/O, Timer 1 inverted channel 2, LCD segment 2, or RTC tamper 2 detection input; 5V tolerant.
21 PE2 bidirectional Port E2 configurable as general purpose I/O, Timer 1 inverted channel 3, LCD segment 3, or RTC tamper 3 detection input; 5V tolerant.
22 PE3 bidirectional Port E3 configurable as general purpose I/O, LCD segment 4, or USART2 receive; 5V tolerant.
23 PE4 bidirectional Port E4 configurable as general purpose I/O, LCD segment 5, or USART2 transmit; 5V tolerant.
24 PE5 bidirectional Port E5 configurable as general purpose I/O, LCD segment 6, ADC1 input channel 23, or USART2 synchronous clock; 5V tolerant.
25 PD0 bidirectional Port D0 configurable as general purpose I/O, Timer 3 channel 2, alternate ADC1 trigger, LCD segment 7, or ADC1 input channel 22; 5V tolerant.
26 PD1 bidirectional Port D1 configurable as general purpose I/O, Timer 3 external trigger, LCD common 3, or ADC1 input channel 21; 5V tolerant.
27 PD2 bidirectional Port D2 configurable as general purpose I/O, Timer 1 channel 1, LCD segment 8, or ADC1 input channel 20; 5V tolerant.
28 PD3 bidirectional Port D3 configurable as general purpose I/O, Timer 1 external trigger, LCD segment 9, or ADC1 input channel 19; 5V tolerant.
29 VDD3 power_in I/O supply voltage; must not be left unconnected; supply range 1.8 to 3.6 V.
30 VSS3 power_in I/O ground return; must not be left unconnected; supply range 1.8 to 3.6 V.
31 PB0 bidirectional Port B0 configurable as general purpose I/O, Timer 2 channel 1, LCD segment 10, or ADC1 input channel 18; 5V tolerant; pull-up applied during reset, input floating after reset release.
32 PB1 bidirectional Port B1 configurable as general purpose I/O, Timer 3 channel 1, LCD segment 11, or ADC1 input channel 17; 5V tolerant.
33 PB2 bidirectional Port B2 configurable as general purpose I/O, Timer 2 channel 2, LCD segment 12, or ADC1 input channel 16; 5V tolerant.
34 PB3 bidirectional Port B3 configurable as general purpose I/O, Timer 2 external trigger, LCD segment 13, or ADC1 input channel 15; 5V tolerant.
35 PB4 bidirectional Port B4 configurable as general purpose I/O, alternate SPI1 master/slave select, LCD segment 14, or ADC1 input channel 14; 5V tolerant; pull-up applied during reset.
36 PB5 bidirectional Port B5 configurable as general purpose I/O, alternate SPI1 clock, LCD segment 15, or ADC1 input channel 13; 5V tolerant.
37 PB6 bidirectional Port B6 configurable as general purpose I/O, alternate SPI1 master out/slave in, LCD segment 16, or ADC1 input channel 12; 5V tolerant.
38 PB7 bidirectional Port B7 configurable as general purpose I/O, alternate SPI1 master in/slave out, LCD segment 17, or ADC1 input channel 11; 5V tolerant.
39 PF0 bidirectional Port F0 configurable as general purpose I/O, ADC1 input channel 24, or alternate USART3 transmit.
40 PF1 bidirectional Port F1 configurable as general purpose I/O, ADC1 input channel 25, or alternate USART3 receive.
41 PF4 bidirectional Port F4 configurable as general purpose I/O, LCD segment 36, or LCD common 4 with SEG/COM multiplexing available; 5V tolerant.
42 PF5 bidirectional Port F5 configurable as general purpose I/O, LCD segment 37, or LCD common 5 with SEG/COM multiplexing available; 5V tolerant.
43 PF6 bidirectional Port F6 configurable as general purpose I/O, LCD segment 38, or LCD common 6 with SEG/COM multiplexing available; 5V tolerant.
44 PF7 bidirectional Port F7 configurable as general purpose I/O, LCD segment 39, or LCD common 7 with SEG/COM multiplexing available; 5V tolerant.
45 PD4 bidirectional Port D4 configurable as general purpose I/O, Timer 1 channel 2, LCD segment 18, or ADC1 input channel 10; 5V tolerant.
46 PD5 bidirectional Port D5 configurable as general purpose I/O, Timer 1 channel 3, LCD segment 19, or ADC1 input channel 9; 5V tolerant.
47 PD6 bidirectional Port D6 configurable as general purpose I/O, Timer 1 break input, LCD segment 20, ADC1 input channel 8, RTC calibration input, or internal voltage reference output; 5V tolerant.
48 PD7 bidirectional Port D7 configurable as general purpose I/O, Timer 1 inverted channel 1, LCD segment 21, ADC1 input channel 7, RTC alarm output, or internal voltage reference output; 5V tolerant.
49 PG4 bidirectional Port G4 configurable as general purpose I/O or SPI2 master/slave select; 5V tolerant.
50 PG5 bidirectional Port G5 configurable as general purpose I/O or SPI2 clock; 5V tolerant.
51 PG6 bidirectional Port G6 configurable as general purpose I/O or SPI2 master out/slave in; 5V tolerant.
52 PG7 bidirectional Port G7 configurable as general purpose I/O or SPI2 master in/slave out; 5V tolerant.
53 PC0 bidirectional Port C0 configurable as general purpose I/O or I2C1 serial data with true open-drain output; 5V tolerant without protection diode to VDD.
54 PC1 bidirectional Port C1 configurable as general purpose I/O or I2C1 serial clock with true open-drain output; 5V tolerant without protection diode to VDD.
55 VDD2 power_in I/O supply voltage; must not be left unconnected; supply range 1.8 to 3.6 V.
56 VSS2 power_in I/O ground return; must not be left unconnected; supply range 1.8 to 3.6 V.
57 PC2 bidirectional Port C2 configurable as general purpose I/O, USART1 receive, LCD segment 22, ADC1 input channel 6, or internal voltage reference output; 5V tolerant.
58 PC3 bidirectional Port C3 configurable as general purpose I/O, USART1 transmit, LCD segment 23, or ADC1 input channel 5; 5V tolerant.
59 PC4 bidirectional Port C4 configurable as general purpose I/O, USART1 synchronous clock, I2C1 SMBus interface, configurable clock output, or ADC1 input channel 4; 5V tolerant.
60 PC5 bidirectional Port C5 configurable as general purpose I/O, LSE oscillator input, alternate SPI1 master/slave select, or alternate USART1 transmit; 5V tolerant.
61 PC6 bidirectional Port C6 configurable as general purpose I/O, LSE oscillator output, alternate SPI1 clock, or alternate USART1 receive; 5V tolerant.
62 PC7 bidirectional Port C7 configurable as general purpose I/O or ADC1 input channel 3; 5V tolerant.
63 PE6 bidirectional Port E6 configurable as general purpose I/O, programmable voltage detector input, or Timer 5 break input; 5V tolerant.
64 PE7 bidirectional Port E7 configurable as general purpose I/O or Timer 5 external trigger; 5V tolerant.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM8L052R8T6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm8l052r8t6-etched.step / stm8l052r8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8l052r8t6.step / stm8l052r8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (55 pp, sha256 c6e456a46f9e5c98, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF