# STM8L050J3M3

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · SOIC-8-150mil

STM8L050J3M3 from STMicroelectronics, in a SOIC-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA0 / PA2 / PC6 | bidirectional | Shared pin bonding three GPIOs: PA0 (USART1 CK, SWIM, BEEP, IR_TIM output, high-sink LED driver capable, input pull-up during reset), PA2 (HSE oscillator input, USART TX, SPI MISO) and PC6 (LSE oscillator output, SPI clock, USART RX, Timer 2 channel 2), and any pull-up or mode setting on one GPIO affects the others on this pin. |
| 2 | PA3 | bidirectional | Port A3 with HSE oscillator output, USART RX and SPI MOSI alternate functions, high sink/source capable (20 mA). |
| 3 | VSS / VREF- / VSSA | power_in | Ground voltage, also the ADC1 negative voltage reference and the analog ground. |
| 4 | VDD / VDDA / VREF+ | power_in | Digital supply voltage, analog supply voltage and ADC1 positive voltage reference. |
| 5 | PB3/TIM2_ETR/ADC1_IN15/RTC_ALARM/COMP1_INP | bidirectional | Shared pin bonding PB3 (Timer 2 external trigger, ADC1_IN15, RTC_ALARM, Comparator 1 positive input), PB5 (SPI clock, ADC1_IN13, Comparator 1 positive input) and PD0 (Timer 3 channel 2, ADC1_IN22, Comparator 1 and 2 positive inputs), all high sink/source capable (20 mA); push-pull configuration of PB3 also affects PB5 and PD0. |
| 6 | PB6 | bidirectional | Port B6 with SPI master out/slave in, ADC1_IN12 and Comparator 1 positive input, high sink/source capable (20 mA). |
| 7 | PB7/SPI_MISO/ADC1_IN11/COMP1_INP | bidirectional | Shared pin bonding PB7 (SPI master in/slave out, ADC1_IN11, Comparator 1 positive input, high sink/source 20 mA) and PC0 (I2C data on a true open-drain output, whose maximum VIN is limited by the standard GPIO PB7 bonded to the same pin). |
| 8 | PC1 / PC4 / PC5 | bidirectional | Shared pin bonding PC1 (I2C clock, true open-drain output, maximum VIN limited by the standard GPIO on the same pin), PC4 (USART synchronous clock, I2C SMBus, configurable clock output, ADC1_IN4, Comparator 1 positive and Comparator 2 negative inputs) and PC5 (LSE oscillator input, SPI NSS, USART TX, Timer 2 channel 1); PC5 and PC6 are the bootloader USART TX and RX pins. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8-150mil |
| Category | Embedded Processors & Controllers |
| Pins | 8 |

## CAD (KiCad official)

- Symbol: `STM8L050J3M3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8-150mil (KiCad packages3D, STEP)
- 3D model files: `stm8l050j3m3-etched.step` / `stm8l050j3m3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8l050j3m3.step` / `stm8l050j3m3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588918058596880384) (94 pp, sha256 `1db17bbbe51fb11c`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm8l050j3m3-datasheet.pdf)