Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM8AL3188TCY

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM8AL3188TCY from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PA0	bidirectional	Port A0 high sink LED driver I/O, input pull-up during reset and after reset release, with alternate functions USART1 synchronous clock, SWIM input/output, Beep output and infrared timer output.
2	NRST/PA1	bidirectional	Reset input with pull-up at power-up (VIL max 0.8 V, VIH min 1.4 V); as general-purpose pin it is PA1, output only (open-drain or push-pull), not usable as a general-purpose input.
3	PA2/OSC_IN	bidirectional	HSE oscillator input with high sink/source I/O and alternate functions USART1 transmit and SPI1 master in/slave out.
4	PA3/OSC_OUT	bidirectional	HSE oscillator output with high sink/source I/O and alternate functions USART1 receive and SPI1 master out/slave in.
5	PA4	bidirectional	Port A4 five-volt tolerant I/O with TIM2 break input, optional TIM2 trigger, ADC1 input 2 and comparator 1 positive input.
6	PA5	bidirectional	Port A5 five-volt tolerant I/O with TIM3 break input, optional TIM3 trigger, ADC1 input 1 and comparator 1 positive input.
7	PA6	bidirectional	Port A6 five-volt tolerant I/O with ADC1 trigger, ADC1 input 0 and comparator 1 positive input.
8	PA7	bidirectional	Port A7 five-volt tolerant I/O with TIM5 channel 1 alternate function.
9	VSS/VSSA/VREF-	power_in	I/O ground, analog ground voltage and ADC1 negative voltage reference.
10	VDD1	power_in	Digital power supply.
11	VDDA	power_in	Analog supply voltage.
12	VREF+/VREF+_DAC	power_in	Positive voltage reference for ADC1 and DAC1/DAC2.
13	VLCD	passive	Reserved on STM8AL318x devices and must be tied to VDD (LCD booster capacitor pin on STM8AL3L8x only).
14	PE0	bidirectional	Port E0 five-volt tolerant I/O with TIM5 channel 2 and RTC tamper 1 alternate functions.
15	PE1	bidirectional	Port E1 five-volt tolerant I/O with TIM1 inverted channel 2 and RTC tamper 2 alternate functions.
16	PE2	bidirectional	Port E2 five-volt tolerant I/O with TIM1 inverted channel 3 and RTC tamper 3 alternate functions.
17	PE3	bidirectional	Port E3 five-volt tolerant I/O with USART2 receive alternate function.
18	PE4	bidirectional	Port E4 five-volt tolerant I/O with DAC 2 trigger and USART2 transmit alternate functions.
19	PE5	bidirectional	Port E5 five-volt tolerant I/O with ADC1 input 23, comparator 1 and 2 positive inputs and USART2 synchronous clock.
20	PD0	bidirectional	Port D0 five-volt tolerant I/O with TIM3 channel 2, optional ADC1 trigger, ADC1 input 22 and comparator 2 positive input 2.
21	PD1	bidirectional	Port D1 five-volt tolerant I/O with TIM3 trigger, ADC1 input 21 and comparator 1 and 2 positive inputs.
22	PD2	bidirectional	Port D2 five-volt tolerant I/O with TIM1 channel 1, ADC1 input 20 and comparator 1 positive input.
23	PD3	bidirectional	Port D3 five-volt tolerant I/O with TIM1 trigger, ADC1 input 19 and comparator 1 positive input.
24	PB0	bidirectional	Port B0 five-volt tolerant I/O with TIM2 channel 1, ADC1 input 18 and comparator 1 positive input; pull-up applied during reset phase, input floating after reset release.
25	PB1	bidirectional	Port B1 five-volt tolerant I/O with TIM3 channel 1, ADC1 input 17 and comparator 1 positive input.
26	PB2	bidirectional	Port B2 five-volt tolerant I/O with TIM2 channel 2, ADC1 input 16 and comparator 1 positive input.
27	PB3	bidirectional	Port B3 five-volt tolerant I/O with TIM2 trigger, ADC1 input 15 and comparator 1 positive input.
28	PB4	bidirectional	Port B4 five-volt tolerant I/O with SPI1 master/slave select, ADC1 input 14, DAC channel 2 output and comparator 1 positive input; pull-up applied during reset phase, input floating after reset release.
29	PB5	bidirectional	Port B5 five-volt tolerant I/O with SPI1 clock, ADC1 input 13, DAC channel 2 output and comparator 1 positive input.
30	PB6	bidirectional	Port B6 five-volt tolerant I/O with SPI1 master out/slave in, ADC1 input 12, DAC channel 2 output and comparator 1 positive input.
31	PB7	bidirectional	Port B7 five-volt tolerant I/O with SPI1 master in/slave out, ADC1 input 11 and comparator 1 positive input.
32	PF0	bidirectional	Port F0 I/O (not five-volt tolerant) with ADC1 input 24 and DAC 1 output.
33	PD4	bidirectional	Port D4 five-volt tolerant I/O with TIM1 channel 2, ADC1 input 10, SPI2 master in/slave out and comparator 1 positive input.
34	PD5	bidirectional	Port D5 five-volt tolerant I/O with TIM1 channel 3, ADC1 input 9, SPI2 master out/slave in and comparator 1 positive input.
35	PD6	bidirectional	Port D6 five-volt tolerant I/O with TIM1 break input, ADC1 input 8, RTC calibration, SPI2 clock, comparator 1 positive input and internal reference voltage output.
36	PD7	bidirectional	Port D7 five-volt tolerant I/O with TIM1 inverted channel 1, ADC1 input 7, RTC alarm, SPI2 master/slave select, comparator 1 positive input and internal reference voltage output.
37	PC0	bidirectional	Port C0 true open-drain I/O (no weak pull-up and no protection diode to VDD) with I2C1 data.
38	PC1	bidirectional	Port C1 true open-drain I/O (no weak pull-up and no protection diode to VDD) with I2C1 clock.
39	VDD2	power_in	IOs supply voltage.
40	VSS2	power_in	IOs ground voltage.
41	PC2	bidirectional	Port C2 five-volt tolerant I/O with USART1 receive, ADC1 input 6, comparator 1 positive input and internal reference voltage output.
42	PC3	bidirectional	Port C3 five-volt tolerant I/O with USART1 transmit and ADC1 input 5.
43	PC4	bidirectional	Port C4 five-volt tolerant I/O with USART1 synchronous clock, I2C1 SMBus, configurable clock output, ADC1 input 4, comparator 2 negative input and comparator 1 positive input.
44	PC5	bidirectional	Port C5 five-volt tolerant I/O with LSE oscillator input (OSC32_IN), SPI1 master/slave select and USART1 transmit alternate functions.
45	PC6	bidirectional	Port C6 five-volt tolerant I/O with LSE oscillator output (OSC32_OUT), SPI1 clock and USART1 receive alternate functions.
46	PC7	bidirectional	Port C7 five-volt tolerant I/O with ADC1 input 3, USART3 synchronous clock, comparator 2 negative input and comparator 1 positive input.
47	PE6	bidirectional	Port E6 five-volt tolerant I/O with PVD input, TIM5 break input and USART3 transmit alternate functions.
48	PE7	bidirectional	Port E7 five-volt tolerant I/O with TIM5 trigger and USART3 receive alternate functions.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

CAD (KiCad official)

Symbol: STM8AL3188TCY
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm8al3188tcy-etched.step / stm8al3188tcy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8al3188tcy.step / stm8al3188tcy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (132 pp, sha256 afd66c9215d8fa58, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF