component
STM8AL3166TCY
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8AL3166TCY
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STM8AL3166TCY from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST/PA1 | bidirectional | Reset input with pull-up at power-up; as PA1 it can be configured only as push-pull output, not as open-drain or general-purpose input. |
| 2 | PA2/OSC_IN/USART1_TX/SPI1_MISO | bidirectional | Port A2 with HSE oscillator input, USART1 transmit and SPI1 master-in/slave-out (bracketed alternates are remap options); high sink/source I/O. |
| 3 | PA3/OSC_OUT/USART1_RX/SPI1_MOSI | bidirectional | Port A3 with HSE oscillator output, USART1 receive and SPI1 master-out/slave-in (bracketed alternates are remap options); high sink/source I/O. |
| 4 | PA4/TIM2_BKIN/TIM2_ETR | bidirectional | Port A4 with TIM2 break input, optional TIM2 trigger, ADC1 input 2 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 5 | PA5/TIM3_BKIN/TIM3_ETR | bidirectional | Port A5 with TIM3 break input, optional TIM3 trigger, ADC1 input 1 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 6 | PA6/ADC1_TRIG | bidirectional | Port A6 with optional ADC1 trigger, ADC1 input 0 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 7 | VSS1/VSSA/VREF- | power_in | I/O ground, analog ground and ADC1 negative voltage reference. |
| 8 | VDD1/VDDA/VREF+ | power_in | Digital power supply, analog supply and ADC1 positive voltage reference; device operating range is 1.8 V to 3.6 V (down to 1.65 V at power down). |
| 9 | PD0/TIM3_CH2/ADC1_TRIG/ADC1_IN22 | bidirectional | Port D0 with TIM3 channel 2, optional ADC1 trigger, ADC1 input 22 and comparator 1 and 2 positive inputs; 3.6 V tolerant (TT) I/O, high sink/source. |
| 10 | PD1/TIM1_CH3N/TIM3_ETR | bidirectional | Port D1 with TIM1 inverted channel 3, optional TIM3 trigger, ADC1 input 21 and comparator 1 and 2 positive inputs; 3.6 V tolerant (TT) I/O, high sink/source. |
| 11 | PD2/TIM1_CH1/ADC1_IN20 | bidirectional | Port D2 with TIM1 channel 1, ADC1 input 20 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 12 | PD3/TIM1_ETR/ADC1_IN19 | bidirectional | Port D3 with TIM1 trigger, ADC1 input 19 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 13 | PB0/TIM2_CH1/ADC1_IN18 | bidirectional | Port B0 with TIM2 channel 1, ADC1 input 18 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source, with a pull-up applied during the reset phase and input floating after reset release. |
| 14 | PB1/TIM3_CH1/ADC1_IN17 | bidirectional | Port B1 with TIM3 channel 1, ADC1 input 17 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 15 | PB2/TIM2_CH2/ADC1_IN16 | bidirectional | Port B2 with TIM2 channel 2, ADC1 input 16 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 16 | PB3/TIM2_ETR/TIM1_CH2N/ADC1_IN15 | bidirectional | Port B3 with optional TIM2 trigger, TIM1 inverted channel 2, ADC1 input 15 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 17 | PB4/SPI1_NSS/ADC1_IN14/DAC_OUT | bidirectional | Port B4 with optional SPI1 master/slave select, ADC1 input 14, DAC output and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source, with a pull-up during the reset phase and input floating after reset release. |
| 18 | PB5/SPI1_SCK/ADC1_IN13/DAC_OUT | bidirectional | Port B5 with optional SPI1 clock, ADC1 input 13, DAC output and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 19 | PB6/SPI1_MOSI/ADC1_IN12/DAC_OUT | bidirectional | Port B6 with optional SPI1 master-out/slave-in, ADC1 input 12, DAC output and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 20 | PB7/SPI1_MISO/ADC1_IN11 | bidirectional | Port B7 with optional SPI1 master-in/slave-out, ADC1 input 11 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 21 | PD4/TIM1_CH2/ADC1_IN10 | bidirectional | Port D4 with TIM1 channel 2, ADC1 input 10 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 22 | PD5/TIM1_CH3/ADC1_IN9 | bidirectional | Port D5 with TIM1 channel 3, ADC1 input 9 and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 23 | PD6/TIM1_BKIN/ADC1_IN8/RTC_CALIB/VREFINT | bidirectional | Port D6 with TIM1 break input, ADC1 input 8, RTC calibration output, internal voltage reference output and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 24 | PD7/TIM1_CH1N/ADC1_IN7/RTC_ALARM/VREFINT | bidirectional | Port D7 with TIM1 inverted channel 1, ADC1 input 7, RTC alarm, internal voltage reference output and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 25 | PC0/I2C1_SDA | bidirectional | Port C0 with I2C1 data; 5 V tolerant (FT) true open-drain I/O without protection diode to VDD and without weak pull-up. |
| 26 | PC1/I2C1_SCL | bidirectional | Port C1 with I2C1 clock; 5 V tolerant (FT) true open-drain I/O without protection diode to VDD and without weak pull-up. |
| 27 | PC2/USART1_RX/ADC1_IN6/VREFINT | bidirectional | Port C2 with USART1 receive, ADC1 input 6, comparator 1 positive input and internal voltage reference output; 3.6 V tolerant (TT) I/O, high sink/source. |
| 28 | PC3/USART1_TX/ADC1_IN5/COMP2_INM | bidirectional | Port C3 with USART1 transmit, ADC1 input 5, comparator 1 positive input and comparator 2 negative input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 29 | PC4/USART1_CK/I2C1_SMB/CCO/ADC1_IN4 | bidirectional | Port C4 with USART1 synchronous clock, I2C1_SMB, configurable clock output, ADC1 input 4, comparator 2 negative input and comparator 1 positive input; 3.6 V tolerant (TT) I/O, high sink/source. |
| 30 | PC5/OSC32_IN/SPI1_NSS/USART1_TX | bidirectional | Port C5 with LSE oscillator input and optional SPI1 master/slave select and USART1 transmit; high sink/source I/O. |
| 31 | PC6/OSC32_OUT/SPI1_SCK/USART1_RX | bidirectional | Port C6 with LSE oscillator output and optional SPI1 clock and USART1 receive; high sink/source I/O. |
| 32 | PA0/USART1_CK/SWIM/BEEP/IR_TIM | bidirectional | Port A0 with optional USART1 synchronous clock, SWIM input and output, beep output and infrared timer output; input pull-up during reset and after reset release, with high sink LED driver capability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
STM8AL3166TCY - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm8al3166tcy-etched.step/stm8al3166tcy-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8al3166tcy.step/stm8al3166tcy.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (123 pp, sha256
c556f7a6ad75fcd6, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).