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STM8AF6288TCX
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+84@@ -0,0 +1,84 @@+# STM8AF6288TCX++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++STM8AF6288TCX from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NRST | bidirectional | Reset pin (NRST); its input and output characteristics are specified in the NRST pin characteristics table (Table 39). |+| 2 | PA1/OSCIN | bidirectional | Port A1 I/O that doubles as the resonator/crystal oscillator input (OSCIN); in Halt/Active-halt the I/O path is disabled and the weak pull-up depends on HSE wakeup use and Px_CR1 settings (footnote 1). |+| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O that doubles as the resonator/crystal oscillator output (OSCOUT). |+| 4 | VSSIO_1 | power_in | I/O ground for the first I/O group. |+| 5 | VSS | power_in | Digital ground. |+| 6 | VCAP | passive | 1.8 V regulator capacitor pin; the external VCAP capacitor is specified in Section 10.3.1. |+| 7 | VDD | power_in | Digital power supply; the device operates from a 3.3 V to 5.5 V supply. |+| 8 | VDDIO_1 | power_in | I/O power supply for the first I/O group. |+| 9 | PA3/TIM2_CH3 | bidirectional | Port A3 I/O with default alternate function Timer 2 channel 3, remappable to TIM3_CH1 via the AFR1 option bit. |+| 10 | PA4/USART_RX | bidirectional | Port A4 I/O with default alternate function USART receive. |+| 11 | PA5/USART_TX | bidirectional | Port A5 I/O with default alternate function USART transmit. |+| 12 | PA6/USART_CK | bidirectional | Port A6 I/O with default alternate function USART synchronous clock output. |+| 13 | VDDA | power_in | Analog power supply for the ADC. |+| 14 | VSSA | power_in | Analog ground. |+| 15 | PB7/AIN7 | bidirectional | Port B7 I/O with ADC analog input 7. |+| 16 | PB6/AIN6 | bidirectional | Port B6 I/O with ADC analog input 6. |+| 17 | PB5/AIN5 | bidirectional | Port B5 I/O with ADC analog input 5; I2C_SDA is available as an alternate function after remap via the AFR6 option bit. |+| 18 | PB4/AIN4 | bidirectional | Port B4 I/O with ADC analog input 4; I2C_SCL is available as an alternate function after remap via the AFR6 option bit. |+| 19 | PB3/AIN3 | bidirectional | Port B3 I/O with ADC analog input 3; TIM1_ETR is available as an alternate function after remap via the AFR5 option bit. |+| 20 | PB2/AIN2 | bidirectional | Port B2 I/O with ADC analog input 2; TIM1_CH3N is available as an alternate function after remap via the AFR5 option bit. |+| 21 | PB1/AIN1 | bidirectional | Port B1 I/O with ADC analog input 1; TIM1_CH2N is available as an alternate function after remap via the AFR5 option bit. |+| 22 | PB0/AIN0 | bidirectional | Port B0 I/O with ADC analog input 0; TIM1_CH1N is available as an alternate function after remap via the AFR5 option bit. |+| 23 | PE7/AIN8 | bidirectional | Port E7 I/O with ADC analog input 8. |+| 24 | PE6/AIN9 | bidirectional | Port E6 I/O with ADC analog input 9. |+| 25 | PE5/SPI_NSS | bidirectional | Port E5 I/O with SPI master/slave select function. |+| 26 | PC1/TIM1_CH1 | bidirectional | Port C1 high-sink I/O (8 mA) with Timer 1 channel 1 function. |+| 27 | PC2/TIM1_CH2 | bidirectional | Port C2 high-sink I/O (8 mA) with Timer 1 channel 2 function. |+| 28 | PC3/TIM1_CH3 | bidirectional | Port C3 high-sink I/O (8 mA) with Timer 1 channel 3 function. |+| 29 | PC4/TIM1_CH4 | bidirectional | Port C4 high-sink I/O (8 mA) with Timer 1 channel 4 function. |+| 30 | PC5/SPI_SCK | bidirectional | Port C5 I/O with SPI clock function. |+| 31 | VSSIO_2 | power_in | I/O ground for the second I/O group. |+| 32 | VDDIO_2 | power_in | I/O power supply for the second I/O group. |+| 33 | PC6/SPI_MOSI | bidirectional | Port C6 I/O with SPI master out / slave in function. |+| 34 | PC7/SPI_MISO | bidirectional | Port C7 I/O with SPI master in / slave out function. |+| 35 | PG0/CAN_TX | bidirectional | Port G0 I/O with CAN transmit function; the CAN interface is only available on STM8AF52xx product lines, not on this STM8AF62xx part. |+| 36 | PG1/CAN_RX | bidirectional | Port G1 I/O with CAN receive function; the CAN interface is only available on STM8AF52xx product lines, not on this STM8AF62xx part. |+| 37 | PE3/TIM1_BKIN | bidirectional | Port E3 I/O with Timer 1 break input function. |+| 38 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain I/O (no weak pull-up and no protection diode to VDD) carrying the I2C data function. |+| 39 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain I/O (no weak pull-up and no protection diode to VDD) carrying the I2C clock function. |+| 40 | PE0/CLK_CCO | bidirectional | Port E0 I/O with configurable clock output (CLK_CCO) function. |+| 41 | PD0/TIM3_CH2 | bidirectional | Port D0 high-sink I/O (8 mA) with Timer 3 channel 2 function; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available as remapped alternate functions. |+| 42 | PD1/SWIM | bidirectional | Port D1 high-sink I/O carrying the SWIM data interface; it is in input pull-up during reset and after reset release. |+| 43 | PD2/TIM3_CH1 | bidirectional | Port D2 high-sink I/O (8 mA) with Timer 3 channel 1 function; TIM2_CH3 is available as a remapped alternate function (AFR1). |+| 44 | PD3/TIM2_CH2 | bidirectional | Port D3 high-sink I/O (8 mA) with Timer 2 channel 2 function; ADC_ETR is available as a remapped alternate function (AFR0). |+| 45 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 high-sink I/O (8 mA) with Timer 2 channel 1 function; BEEP output is available as a remapped alternate function (AFR7). |+| 46 | PD5/LINUART_TX | bidirectional | Port D5 I/O with LINUART data transmit function. |+| 47 | PD6/LINUART_RX | bidirectional | Port D6 I/O with LINUART data receive function. |+| 48 | PD7/TLI | bidirectional | Port D7 I/O with top level interrupt (TLI) function; if configured as an interrupt pin it triggers the TLI. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-48(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `STM8AF6288TCX`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `stm8af6288tcx-etched.step` / `stm8af6288tcx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8af6288tcx.step` / `stm8af6288tcx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm8af6288tcx.pdf) (125 pp, sha256 `3f11cfe069d4bf98`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm8af6288tcx-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "stm8af6288tcx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "stm8af6288tcx.kicad_sym",+ "stm8af6288tcx.kicad_mod",+ "stm8af6288tcx.glb",+ "stm8af6288tcx.step",+ "stm8af6288tcx.lbr",+ "docs/hero.png",+ "docs/stm8af6288tcx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "stm8af6288tcx-hero.glb",+ "stm8af6288tcx-hero.overlay.json"+ ],+ "component": {+ "mpn": "STM8AF6288TCX",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.st.com/resource/en/datasheet/stm8af6288tcx.pdf",+ "parts": {+ "symbol": "stm8af6288tcx.kicad_sym",+ "footprint": "stm8af6288tcx.kicad_mod",+ "model_3d": "stm8af6288tcx-hero.glb",+ "model_3d_plain": "stm8af6288tcx.glb",+ "model_3d_step": "stm8af6288tcx-etched.step",+ "model_3d_step_plain": "stm8af6288tcx.step",+ "lbr": "stm8af6288tcx.lbr"+ },+ "distributor_links": {+ "lcsc": "C2965237",+ "digikey": "STM8AF6288TCX-ND",+ "mouser": "511-STM8AF6288TCX"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:53:03Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "STM8AF6288TCX-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-STM8AF6288TCX",+ "status": "found",+ "lifecycle": "End of Life"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NRST",+ "type": "bidirectional",+ "description": "Reset pin (NRST); its input and output characteristics are specified in the NRST pin characteristics table (Table 39)."+ },+ {+ "number": "2",+ "name": "PA1/OSCIN",+ "type": "bidirectional",+ "description": "Port A1 I/O that doubles as the resonator/crystal oscillator input (OSCIN); in Halt/Active-halt the I/O path is disabled and the weak pull-up depends on HSE wakeup use and Px_CR1 settings (footnote 1)."+ },+ {+ "number": "3",+ "name": "PA2/OSCOUT",+ "type": "bidirectional",+ "description": "Port A2 I/O that doubles as the resonator/crystal oscillator output (OSCOUT)."+ },+ {+ "number": "4",+ "name": "VSSIO_1",+ "type": "power_in",+ "description": "I/O ground for the first I/O group."+ },+ {+ "number": "5",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "6",+ "name": "VCAP",+ "type": "passive",+ "description": "1.8 V regulator capacitor pin; the external VCAP capacitor is specified in Section 10.3.1."+ },+ {+ "number": "7",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital power supply; the device operates from a 3.3 V to 5.5 V supply."+ },+ {+ "number": "8",+ "name": "VDDIO_1",+ "type": "power_in",+ "description": "I/O power supply for the first I/O group."+ },+ {+ "number": "9",+ "name": "PA3/TIM2_CH3",+ "type": "bidirectional",+ "description": "Port A3 I/O with default alternate function Timer 2 channel 3, remappable to TIM3_CH1 via the AFR1 option bit."+ },+ {+ "number": "10",+ "name": "PA4/USART_RX",+ "type": "bidirectional",+ "description": "Port A4 I/O with default alternate function USART receive."+ },+ {+ "number": "11",+ "name": "PA5/USART_TX",+ "type": "bidirectional",+ "description": "Port A5 I/O with default alternate function USART transmit."+ },+ {+ "number": "12",+ "name": "PA6/USART_CK",+ "type": "bidirectional",+ "description": "Port A6 I/O with default alternate function USART synchronous clock output."+ },+ {+ "number": "13",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply for the ADC."+ },+ {+ "number": "14",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "15",+ "name": "PB7/AIN7",+ "type": "bidirectional",+ "description": "Port B7 I/O with ADC analog input 7."+ },+ {+ "number": "16",+ "name": "PB6/AIN6",+ "type": "bidirectional",+ "description": "Port B6 I/O with ADC analog input 6."+ },+ {+ "number": "17",+ "name": "PB5/AIN5",+ "type": "bidirectional",+ "description": "Port B5 I/O with ADC analog input 5; I2C_SDA is available as an alternate function after remap via the AFR6 option bit."+ },+ {+ "number": "18",+ "name": "PB4/AIN4",+ "type": "bidirectional",+ "description": "Port B4 I/O with ADC analog input 4; I2C_SCL is available as an alternate function after remap via the AFR6 option bit."+ },+ {+ "number": "19",+ "name": "PB3/AIN3",+ "type": "bidirectional",+ "description": "Port B3 I/O with ADC analog input 3; TIM1_ETR is available as an alternate function after remap via the AFR5 option bit."+ },+ {+ "number": "20",+ "name": "PB2/AIN2",+ "type": "bidirectional",+ "description": "Port B2 I/O with ADC analog input 2; TIM1_CH3N is available as an alternate function after remap via the AFR5 option bit."+ },+ {+ "number": "21",+ "name": "PB1/AIN1",+ "type": "bidirectional",+ "description": "Port B1 I/O with ADC analog input 1; TIM1_CH2N is available as an alternate function after remap via the AFR5 option bit."+ },+ {+ "number": "22",+ "name": "PB0/AIN0",+ "type": "bidirectional",+ "description": "Port B0 I/O with ADC analog input 0; TIM1_CH1N is available as an alternate function after remap via the AFR5 option bit."+ },+ {+ "number": "23",+ "name": "PE7/AIN8",+ "type": "bidirectional",+ "description": "Port E7 I/O with ADC analog input 8."+ },+ {+ "number": "24",+ "name": "PE6/AIN9",+ "type": "bidirectional",+ "description": "Port E6 I/O with ADC analog input 9."+ },+ {+ "number": "25",+ "name": "PE5/SPI_NSS",+ "type": "bidirectional",+ "description": "Port E5 I/O with SPI master/slave select function."+ },+ {+ "number": "26",+ "name": "PC1/TIM1_CH1",+ "type": "bidirectional",+ "description": "Port C1 high-sink I/O (8 mA) with Timer 1 channel 1 function."+ },+ {+ "number": "27",+ "name": "PC2/TIM1_CH2",+ "type": "bidirectional",+ "description": "Port C2 high-sink I/O (8 mA) with Timer 1 channel 2 function."+ },+ {+ "number": "28",+ "name": "PC3/TIM1_CH3",+ "type": "bidirectional",+ "description": "Port C3 high-sink I/O (8 mA) with Timer 1 channel 3 function."+ },+ {+ "number": "29",+ "name": "PC4/TIM1_CH4",+ "type": "bidirectional",+ "description": "Port C4 high-sink I/O (8 mA) with Timer 1 channel 4 function."+ },+ {+ "number": "30",+ "name": "PC5/SPI_SCK",+ "type": "bidirectional",+ "description": "Port C5 I/O with SPI clock function."+ },+ {+ "number": "31",+ "name": "VSSIO_2",+ "type": "power_in",+ "description": "I/O ground for the second I/O group."+ },+ {+ "number": "32",+ "name": "VDDIO_2",+ "type": "power_in",+ "description": "I/O power supply for the second I/O group."+ },+ {+ "number": "33",+ "name": "PC6/SPI_MOSI",+ "type": "bidirectional",+ "description": "Port C6 I/O with SPI master out / slave in function."+ },+ {+ "number": "34",+ "name": "PC7/SPI_MISO",+ "type": "bidirectional",+ "description": "Port C7 I/O with SPI master in / slave out function."+ },+ {+ "number": "35",+ "name": "PG0/CAN_TX",+ "type": "bidirectional",+ "description": "Port G0 I/O with CAN transmit function; the CAN interface is only available on STM8AF52xx product lines, not on this STM8AF62xx part."+ },+ {+ "number": "36",+ "name": "PG1/CAN_RX",+ "type": "bidirectional",+ "description": "Port G1 I/O with CAN receive function; the CAN interface is only available on STM8AF52xx product lines, not on this STM8AF62xx part."+ },+ {+ "number": "37",+ "name": "PE3/TIM1_BKIN",+ "type": "bidirectional",+ "description": "Port E3 I/O with Timer 1 break input function."+ },+ {+ "number": "38",+ "name": "PE2/I2C_SDA",+ "type": "bidirectional",+ "description": "Port E2 true open-drain I/O (no weak pull-up and no protection diode to VDD) carrying the I2C data function."+ },+ {+ "number": "39",+ "name": "PE1/I2C_SCL",+ "type": "bidirectional",+ "description": "Port E1 true open-drain I/O (no weak pull-up and no protection diode to VDD) carrying the I2C clock function."+ },+ {+ "number": "40",+ "name": "PE0/CLK_CCO",+ "type": "bidirectional",+ "description": "Port E0 I/O with configurable clock output (CLK_CCO) function."+ },+ {+ "number": "41",+ "name": "PD0/TIM3_CH2",+ "type": "bidirectional",+ "description": "Port D0 high-sink I/O (8 mA) with Timer 3 channel 2 function; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available as remapped alternate functions."+ },+ {+ "number": "42",+ "name": "PD1/SWIM",+ "type": "bidirectional",+ "description": "Port D1 high-sink I/O carrying the SWIM data interface; it is in input pull-up during reset and after reset release."+ },+ {+ "number": "43",+ "name": "PD2/TIM3_CH1",+ "type": "bidirectional",+ "description": "Port D2 high-sink I/O (8 mA) with Timer 3 channel 1 function; TIM2_CH3 is available as a remapped alternate function (AFR1)."+ },+ {+ "number": "44",+ "name": "PD3/TIM2_CH2",+ "type": "bidirectional",+ "description": "Port D3 high-sink I/O (8 mA) with Timer 2 channel 2 function; ADC_ETR is available as a remapped alternate function (AFR0)."+ },+ {+ "number": "45",+ "name": "PD4/TIM2_CH1/BEEP",+ "type": "bidirectional",+ "description": "Port D4 high-sink I/O (8 mA) with Timer 2 channel 1 function; BEEP output is available as a remapped alternate function (AFR7)."+ },+ {+ "number": "46",+ "name": "PD5/LINUART_TX",+ "type": "bidirectional",+ "description": "Port D5 I/O with LINUART data transmit function."+ },+ {+ "number": "47",+ "name": "PD6/LINUART_RX",+ "type": "bidirectional",+ "description": "Port D6 I/O with LINUART data receive function."+ },+ {+ "number": "48",+ "name": "PD7/TLI",+ "type": "bidirectional",+ "description": "Port D7 I/O with top level interrupt (TLI) function; if configured as an interrupt pin it triggers the TLI."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: PG0/CAN_TX and PG1/CAN_RX are listed in the shared Table 11 and Figure 5, but the datasheet states t; The datasheet gives VCAP as a supply-class pin (type S) for a 1.8 V regulator capacitor. Mapped to K; Table 11 lists NRST, PA1/OSCIN and PA2/OSCOUT as generic 'I/O'. Mapped to bidirectional per the tabl"+ ],+ "pages_sent": 60,+ "cost_usd": 0.2632,+ "at": "2026-10-08T18:52:10"+ },+ "datasheet": {+ "url": "https://www.st.com/resource/en/datasheet/stm8af6288tcx.pdf",+ "pages": 125,+ "sha256": "3f11cfe069d4bf98",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm8af6288tcx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm8af6288tcx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f535dd902d92c56a34c2f4fd1c2da18574b56c85ff0c524586622016765e4191",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}