# STM8AF6246TDSSSX

**STMicroelectronics** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-32(7x7)

STM8AF6246TDSSSX from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin (I/O) used to reset the device; its reset-pin characteristics (filtering, pull-up, input levels) are specified separately in the NRST pin characteristics section. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O that doubles as the resonator/crystal input (OSCIN); in Halt/Active-halt the input/output path is disabled and the pad must not be left floating. |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O that doubles as the resonator/crystal output (OSCOUT); in Halt/Active-halt the input/output path is disabled and the pad must not be left floating. |
| 4 | VSS | power_in | Digital ground of the device. |
| 5 | VCAP | passive | Connection for the 1.8 V regulator capacitor; the external capacitor value is given in the VCAP external capacitor section. |
| 6 | VDD | power_in | Digital power supply of the device. |
| 7 | VDDIO_1 | power_in | I/O power supply for the first group of I/O pins. |
| 8 | PF4/AIN12 | bidirectional | Port F4 I/O and ADC analog input 12; a pull-up from the I/O static characteristics is enabled during reset, and AIN12 is not selectable in ADC scan mode or with the analog watchdog. |
| 9 | VDDA | power_in | Analog power supply for the ADC. |
| 10 | VSSA | power_in | Analog ground for the ADC. |
| 11 | PB5/AIN5 | bidirectional | Port B5 I/O and ADC analog input 5; I2C_SDA is available on this pin when the AFR6 remap option is active. |
| 12 | PB4/AIN4 | bidirectional | Port B4 I/O and ADC analog input 4; I2C_SCL is available on this pin when the AFR6 remap option is active. |
| 13 | PB3/AIN3 | bidirectional | Port B3 I/O and ADC analog input 3; TIM1_ETR is available on this pin when the AFR5 remap option is active. |
| 14 | PB2/AIN2 | bidirectional | Port B2 I/O and ADC analog input 2; TIM1_CH3N is available on this pin when the AFR5 remap option is active. |
| 15 | PB1/AIN1 | bidirectional | Port B1 I/O and ADC analog input 1; TIM1_CH2N is available on this pin when the AFR5 remap option is active. |
| 16 | PB0/AIN0 | bidirectional | Port B0 I/O and ADC analog input 0; TIM1_CH1N is available on this pin when the AFR5 remap option is active. |
| 17 | PE5/SPI_NSS | bidirectional | Port E5 I/O used as the SPI master/slave select (NSS) signal. |
| 18 | PC1/TIM1_CH1 | bidirectional | Port C1 high-sink (8 mA) I/O used as Timer 1 channel 1. |
| 19 | PC2/TIM1_CH2 | bidirectional | Port C2 high-sink (8 mA) I/O used as Timer 1 channel 2. |
| 20 | PC3/TIM1_CH3 | bidirectional | Port C3 high-sink (8 mA) I/O used as Timer 1 channel 3. |
| 21 | PC4/TIM1_CH4 | bidirectional | Port C4 high-sink (8 mA) I/O used as Timer 1 channel 4. |
| 22 | PC5/SPI_SCK | bidirectional | Port C5 I/O used as the SPI clock. |
| 23 | PC6/SPI_MOSI | bidirectional | Port C6 I/O used as the SPI master out / slave in data line. |
| 24 | PC7/SPI_MISO | bidirectional | Port C7 I/O used as the SPI master in / slave out data line. |
| 25 | PD0/TIM3_CH2 | bidirectional | Port D0 high-sink (8 mA) I/O used as Timer 3 channel 2; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available as remap options. |
| 26 | PD1/SWIM | bidirectional | Port D1 high-sink (8 mA) I/O used as the SWIM data interface; the pin is input pull-up during reset and after reset release. |
| 27 | PD2/TIM3_CH1 | bidirectional | Port D2 high-sink (8 mA) I/O used as Timer 3 channel 1; TIM2_CH3 is available as the AFR1 remap option. |
| 28 | PD3/TIM2_CH2 | bidirectional | Port D3 high-sink (8 mA) I/O used as Timer 2 channel 2; ADC_ETR is available as the AFR0 remap option. |
| 29 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 high-sink (8 mA) I/O used as Timer 2 channel 1 or the BEEP output. |
| 30 | PD5/LINUART_TX | bidirectional | Port D5 I/O used as the LINUART data transmit output. |
| 31 | PD6/LINUART_RX | bidirectional | Port D6 I/O used as the LINUART data receive input. |
| 32 | PD7/TLI | bidirectional | Port D7 I/O used as the top-level interrupt (TLI); if configured as an interrupt pin it triggers the TLI. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-32(7x7) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 32 |

## CAD (KiCad official)

- Symbol: `STM8AF6246TDSSSX`
- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`
- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm8af6246tdsssx-etched.step` / `stm8af6246tdsssx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8af6246tdsssx.step` / `stm8af6246tdsssx.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588943008925929472) (99 pp, sha256 `b2515811c84033b5`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm8af6246tdsssx-datasheet.pdf)