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Contents

README

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STM8AF6223PAU

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · TSSOP-20

STM8AF6223PAU from STMicroelectronics, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD4/TIM5_CH1/BEEP/[LINUART_CK] bidirectional Port D4 general-purpose I/O with high-sink drive (up to 20 mA). Default alternate function is TIM5 channel 1 / BEEP output. Remappable to LINUART clock (LINUART_CK) via option bit AFR2.
2 PD5/AIN5/LINUART_TX bidirectional Port D5 high-sink I/O. Doubles as ADC analog input AIN5 and LINUART data transmit (TX).
3 PD6/AIN6/LINUART_RX bidirectional Port D6 high-sink I/O. Doubles as ADC analog input AIN6 and LINUART data receive (RX).
4 NRST bidirectional Active-low bidirectional reset pin with internal weak pull-up. Drive low externally to reset the MCU; the pin is also driven low by internal reset sources.
5 PA1/OSCIN bidirectional Port A1 general-purpose I/O; also HSE crystal/resonator input (OSCIN) or external clock input. Slow-slew (up to 2 MHz) output driver.
6 PA2/OSCOUT bidirectional Port A2 general-purpose I/O; also HSE crystal/resonator output (OSCOUT). Slow-slew (up to 2 MHz) output driver.
7 VSS power_in Digital ground reference (0 V) for the MCU core and I/O.
8 VCAP passive 1.8 V internal regulator decoupling pin. Connect an external ceramic capacitor (typ. 470 nF - 1 µF) to VSS; do not drive externally.
9 VDD power_in Main digital power supply, 3.0 to 5.5 V operating range (absolute max 6.0 V). Also supplies the ADC reference internally.
10 PA3/TIM5_CH3/[SPI_NSS] bidirectional Port A3 high-sink I/O. Default alternate function TIM5 channel 3; remappable to SPI master/slave select (SPI_NSS) via option bit AFR1.
11 PB5/I2C_SDA/[TIM1_BKIN] bidirectional Port B5 true open-drain I/O (no P-buffer, no weak pull-up, no protection diode to VDD). Default alternate function I²C data (SDA); remappable to TIM1 break input via option bit AFR4. Requires external pull-up to VDD.
12 PB4/I2C_SCL/[ADC_ETR] bidirectional Port B4 true open-drain I/O. Default alternate function I²C clock (SCL); remappable to ADC external trigger (ADC_ETR) via option bit AFR4. Requires external pull-up to VDD.
13 PC3/TIM1_CH3/[TLI]/[TIM1_CH1N] bidirectional Port C3 high-sink I/O. Default alternate function TIM1 channel 3; remappable to Top-Level Interrupt (TLI) via option bit AFR3, or to TIM1 inverted channel 1 (CH1N) via AFR7.
14 PC4/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N] bidirectional Port C4 high-sink I/O. Default alternate functions TIM1 channel 4 and configurable clock output (CCO). Also serves as ADC analog input AIN2 (via AFR2) and remappable to TIM1 inverted channel 2 (CH2N) via AFR7.
15 PC5/SPI_SCK/[TIM5_CH1] bidirectional Port C5 high-sink I/O. Default alternate function SPI clock (SCK); remappable to TIM5 channel 1 via option bit AFR0.
16 PC6/SPI_MOSI/[TIM1_CH1] bidirectional Port C6 high-sink I/O. Default alternate function SPI MOSI (master-out/slave-in); remappable to TIM1 channel 1 via option bit AFR0.
17 PC7/SPI_MISO/[TIM1_CH2] bidirectional Port C7 high-sink I/O. Default alternate function SPI MISO (master-in/slave-out); remappable to TIM1 channel 2 via option bit AFR0.
18 PD1/SWIM bidirectional Port D1 high-sink I/O; also the SWIM (Single-Wire Interface Module) data pin used for in-circuit debug and Flash programming. Held in input pull-up during and after reset.
19 PD2/AIN3/[TIM5_CH3] bidirectional Port D2 high-sink I/O. Serves as ADC analog input AIN3 (via AFR2) and remappable to TIM5 channel 3 via option bit AFR1.
20 PD3/AIN4/TIM5_CH2/ADC_ETR bidirectional Port D3 high-sink I/O. Default alternate functions ADC analog input AIN4, TIM5 channel 2, and ADC external trigger (ADC_ETR).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TSSOP-20
Category Embedded Processors & Controllers
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • STM8AF6223PAU
  • STM8AF6223PAY
  • STM8AF6223PAX
  • STM8AF6223PCU
  • STM8AF6223PCY
  • STM8AF6223PCX
  • STM8AF6223PDU
  • STM8AF6223PDY
  • STM8AF6223PDX
  • STM8AF6213PxA/C/Dx
  • STM8AF6223PxAx
  • STM8AF6213PxAx
  • STM8AF6226TAx
  • STM8AF6226TCx
  • STM8AF6226TDx
  • STM8AF6226UAx
  • STM8AF6226UCx
  • STM8AF6226UDx

CAD (KiCad official)

  • Symbol: STM8AF6223PAU
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: stm8af6223pau-etched.step / stm8af6223pau-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8af6223pau.step / stm8af6223pau.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 d9cd5dcf0815e39e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF