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STM8AF52A9TDY

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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STM8AF52A9TDY

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM8AF52A9TDY from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Reset pin with an internal weak pull-up; its electrical characteristics are given in Table 39 (NRST pin characteristics).
2 PA1/OSCIN bidirectional Port A1 I/O (standard speed up to 2 MHz, CMOS input, weak pull-up option) that doubles as the resonator/crystal oscillator input OSCIN.
3 PA2/OSCOUT bidirectional Port A2 I/O (standard speed up to 2 MHz, CMOS input, weak pull-up option) that doubles as the resonator/crystal oscillator output OSCOUT.
4 VSSIO_1 power_in I/O ground for the I/O power domain.
5 VSS power_in Digital ground.
6 VCAP passive 1.8 V regulator capacitor pin, which requires the external VCAP capacitor described in section 10.3.1.
7 VDD power_in Digital power supply.
8 VDDIO_1 power_in I/O power supply.
9 PA3/TIM2_CH3 bidirectional Port A3 I/O (standard speed up to 2 MHz) whose default alternate function is Timer 2 channel 3; TIM3_CH1 is available after AFR1 remap.
10 PA4/USART_RX bidirectional Port A4 I/O (fast/slow programmable speed, slow by default) with USART receive function.
11 PA5/USART_TX bidirectional Port A5 I/O (fast/slow programmable speed, slow by default) with USART transmit function.
12 PA6/USART_CK bidirectional Port A6 I/O (fast/slow programmable speed, slow by default) with USART synchronous clock function.
13 PF7/AIN15 bidirectional Port F7 I/O (standard speed up to 2 MHz) with ADC analog input 15.
14 PF6/AIN14 bidirectional Port F6 I/O (standard speed up to 2 MHz) with ADC analog input 14.
15 PF5/AIN13 bidirectional Port F5 I/O (standard speed up to 2 MHz) with ADC analog input 13.
16 PF4/AIN12 bidirectional Port F4 I/O (standard speed up to 2 MHz) with ADC analog input 12.
17 PF3/AIN11 bidirectional Port F3 I/O (standard speed up to 2 MHz) with ADC analog input 11.
18 VREF+ power_in ADC positive reference voltage.
19 VDDA power_in Analog power supply.
20 VSSA power_in Analog ground.
21 VREF- power_in ADC negative reference voltage.
22 PF0/AIN10 bidirectional Port F0 I/O (standard speed up to 2 MHz) with ADC analog input 10.
23 PB7/AIN7 bidirectional Port B7 I/O (standard speed up to 2 MHz) with ADC analog input 7.
24 PB6/AIN6 bidirectional Port B6 I/O (standard speed up to 2 MHz) with ADC analog input 6.
25 PB5/AIN5 bidirectional Port B5 I/O (standard speed up to 2 MHz) with ADC analog input 5; I2C_SDA is available after AFR6 remap.
26 PB4/AIN4 bidirectional Port B4 I/O (standard speed up to 2 MHz) with ADC analog input 4; I2C_SCL is available after AFR6 remap.
27 PB3/AIN3 bidirectional Port B3 I/O (standard speed up to 2 MHz) with ADC analog input 3; TIM1_ETR is available after AFR5 remap.
28 PB2/AIN2 bidirectional Port B2 I/O (standard speed up to 2 MHz) with ADC analog input 2; TIM1_CH3N is available after AFR5 remap.
29 PB1/AIN1 bidirectional Port B1 I/O (standard speed up to 2 MHz) with ADC analog input 1; TIM1_CH2N is available after AFR5 remap.
30 PB0/AIN0 bidirectional Port B0 I/O (standard speed up to 2 MHz) with ADC analog input 0; TIM1_CH1N is available after AFR5 remap.
31 PE7/AIN8 bidirectional Port E7 I/O (standard speed up to 2 MHz) with ADC analog input 8.
32 PE6/AIN9 bidirectional Port E6 I/O (standard speed up to 2 MHz) with ADC analog input 9.
33 PE5/SPI_NSS bidirectional Port E5 I/O (standard speed up to 2 MHz) with SPI master/slave select function.
34 PC1/TIM1_CH1 bidirectional Port C1 high sink I/O (8 mA, fast/slow programmable speed) with Timer 1 channel 1.
35 PC2/TIM1_CH2 bidirectional Port C2 high sink I/O (8 mA, fast/slow programmable speed) with Timer 1 channel 2.
36 PC3/TIM1_CH3 bidirectional Port C3 high sink I/O (8 mA, fast/slow programmable speed) with Timer 1 channel 3.
37 PC4/TIM1_CH4 bidirectional Port C4 high sink I/O (8 mA, fast/slow programmable speed) with Timer 1 channel 4.
38 PC5/SPI_SCK bidirectional Port C5 I/O (fast/slow programmable speed, slow by default) with SPI clock function.
39 VSSIO_2 power_in I/O ground for the second I/O power domain.
40 VDDIO_2 power_in I/O power supply for the second I/O power domain.
41 PC6/SPI_MOSI bidirectional Port C6 I/O (fast/slow programmable speed, slow by default) with SPI master out / slave in function.
42 PC7/SPI_MISO bidirectional Port C7 I/O (fast/slow programmable speed, slow by default) with SPI master in / slave out function.
43 PG0/CAN_TX bidirectional Port G0 I/O (standard speed up to 2 MHz) with CAN transmit function, available on STM8AF52xx devices.
44 PG1/CAN_RX bidirectional Port G1 I/O (standard speed up to 2 MHz) with CAN receive function, available on STM8AF52xx devices.
45 PG2 bidirectional Port G2 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
46 PG3 bidirectional Port G3 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
47 PG4 bidirectional Port G4 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
48 PI0 bidirectional Port I0 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
49 PG5 bidirectional Port G5 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
50 PG6 bidirectional Port G6 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
51 PG7 bidirectional Port G7 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
52 PE4 bidirectional Port E4 general-purpose I/O (standard speed up to 2 MHz) with no alternate function listed in Table 11.
53 PE3/TIM1_BKIN bidirectional Port E3 I/O (standard speed up to 2 MHz) with Timer 1 break input function.
54 PE2/I2C_SDA bidirectional Port E2 true open-drain I/O (no weak pull-up and no protection diode to VDD) carrying the I2C data line I2C_SDA.
55 PE1/I2C_SCL bidirectional Port E1 true open-drain I/O (no weak pull-up and no protection diode to VDD) carrying the I2C clock line I2C_SCL.
56 PE0/CLK_CCO bidirectional Port E0 I/O (fast/slow programmable speed, slow by default) with configurable clock output CLK_CCO.
57 PD0/TIM3_CH2 bidirectional Port D0 high sink I/O (8 mA, fast/slow programmable speed) with Timer 3 channel 2; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available after remap.
58 PD1/SWIM bidirectional Port D1 high sink I/O (8 mA) used as the SWIM data interface, held in input pull-up during reset phase and after reset release.
59 PD2/TIM3_CH1 bidirectional Port D2 high sink I/O (8 mA, fast/slow programmable speed) with Timer 3 channel 1; TIM2_CH3 is available after AFR1 remap.
60 PD3/TIM2_CH2 bidirectional Port D3 high sink I/O (8 mA, fast/slow programmable speed) with Timer 2 channel 2; ADC_ETR is available after AFR0 remap.
61 PD4/TIM2_CH1/BEEP bidirectional Port D4 high sink I/O (8 mA, fast/slow programmable speed) with Timer 2 channel 1; BEEP output is available after AFR7 remap.
62 PD5/LINUART_TX bidirectional Port D5 I/O (standard speed up to 2 MHz) with LINUART data transmit function.
63 PD6/LINUART_RX bidirectional Port D6 I/O (standard speed up to 2 MHz) with LINUART data receive function.
64 PD7/TLI bidirectional Port D7 I/O (standard speed up to 2 MHz) with top level interrupt TLI; if configured as an interrupt pin it triggers the TLI.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM8AF52A9TDY
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm8af52a9tdy-etched.step / stm8af52a9tdy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8af52a9tdy.step / stm8af52a9tdy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (125 pp, sha256 3f11cfe069d4bf98, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF