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STM804TM6F
Public Made by Adomby adom
STMicroelectronics Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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STM804TM6F
STMicroelectronics · Supervisor And Reset ICs · SOIC-8
STM804TM6F from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Supply output for external LPSRAM: it connects to VCC through a P-channel switch while VCC is above the switchover voltage VSO, switches to VBAT when VCC falls below VSO, and should be tied to VCC if no battery is used. |
| 2 | VCC | power_in | Supply voltage input; RST is asserted whenever VCC falls below the reset threshold VRST, and RST is guaranteed valid down to VCC = 1 V when no backup battery is used. |
| 3 | VSS | power_in | Ground reference for the device. |
| 4 | PFI | input | Power-fail input: when PFI is below VPFI, PFO goes low; connect to ground if unused. |
| 5 | PFO | output | Power-fail output (push-pull) that goes low when PFI is below VPFI or when VCC falls below VSW (2.4 V); leave open if unused. |
| 6 | WDI | input | Watchdog input: if WDI remains high or low for 1.6 s (typ) a reset is triggered, and the watchdog cannot be disabled by letting the pin float. |
| 7 | RST | output | Active-high reset output (open drain) that is high whenever VCC is above the reset threshold or the watchdog has not timed out, pulsing high for trec when triggered and remaining high for trec after VCC falls below the reset threshold. |
| 8 | VBAT | power_in | Backup battery input that connects to VOUT when VCC falls below VSO and disconnects when VCC rises above VSO plus hysteresis; VBAT may exceed VCC, and it should be tied to VCC if no battery is used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
STM804TM6F - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
stm804tm6f-etched.step/stm804tm6f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm804tm6f.step/stm804tm6f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (42 pp, sha256
7b0e1b14da4b9b31, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM804TM6F
**STMicroelectronics** · Supervisor And Reset ICs · SOIC-8
STM804TM6F from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Supply output for external LPSRAM: it connects to VCC through a P-channel switch while VCC is above the switchover voltage VSO, switches to VBAT when VCC falls below VSO, and should be tied to VCC if no battery is used. |
| 2 | VCC | power_in | Supply voltage input; RST is asserted whenever VCC falls below the reset threshold VRST, and RST is guaranteed valid down to VCC = 1 V when no backup battery is used. |
| 3 | VSS | power_in | Ground reference for the device. |
| 4 | PFI | input | Power-fail input: when PFI is below VPFI, PFO goes low; connect to ground if unused. |
| 5 | PFO | output | Power-fail output (push-pull) that goes low when PFI is below VPFI or when VCC falls below VSW (2.4 V); leave open if unused. |
| 6 | WDI | input | Watchdog input: if WDI remains high or low for 1.6 s (typ) a reset is triggered, and the watchdog cannot be disabled by letting the pin float. |
| 7 | RST | output | Active-high reset output (open drain) that is high whenever VCC is above the reset threshold or the watchdog has not timed out, pulsing high for trec when triggered and remaining high for trec after VCC falls below the reset threshold. |
| 8 | VBAT | power_in | Backup battery input that connects to VOUT when VCC falls below VSO and disconnects when VCC rises above VSO plus hysteresis; VBAT may exceed VCC, and it should be tied to VCC if no battery is used. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `STM804TM6F`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `stm804tm6f-etched.step` / `stm804tm6f-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm804tm6f.step` / `stm804tm6f.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942667752988672) (42 pp, sha256 `7b0e1b14da4b9b31`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm804tm6f-datasheet.pdf)