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STM706SM6F
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STMicroelectronics Monitors & Reset Circuits, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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STM706SM6F
STMicroelectronics · Monitors & Reset Circuits · SOIC-8
STM706SM6F from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low push-button reset input with internal 40 kΩ pull-up that asserts reset while low and for trec (140 to 280 ms) after it returns high; may be left open if unused. |
| 2 | VCC | power_in | Supply voltage input monitored against the reset threshold (STM706S: 2.85 to 3.00 V), with absolute maximum of 7.0 V and operating range up to 5.5 V. |
| 3 | VSS | power_in | Ground. |
| 4 | PFI | input | Power-fail comparator input that drives PFO low when below the VPFI threshold (1.25 V typ.); connect to ground if unused. |
| 5 | PFO | output | Push-pull power-fail output that goes low when PFI is below VPFI and stays high otherwise; leave open if unused and do not force it low from a processor. |
| 6 | WDI | input | Watchdog input where a high or low level lasting 1.6 s (typ.) without an edge triggers WDO, and the timer clears on any rising or falling edge or while reset is asserted. |
| 7 | RST | output | Active-low reset output that stays low whenever VCC is below the reset threshold or MR is low, and remains low for trec (200 ms typ.) afterwards. |
| 8 | WDO | output | Push-pull watchdog output that goes low when WDI has no transition within 1.6 s or when VCC falls below the reset threshold, and returns high on a WDI transition, MR low, or as soon as VCC exceeds the threshold. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reset threshold (VCC falling), STM70xS | VRST | 2.85 | 2.93 | 3 | V | For VCC falling | 25 |
| RST pulse width (blank option) | trec | 140 | 200 | 280 | ms | Blank (see Table 9) | 25 |
| Watchdog timeout period | tWD | 1.12 | 1.6 | 2.24 | s | STM70xS/70xT, VCC = 3.3 V | 25 |
| PFI input threshold | VPFI | 1.2 | 1.25 | 1.3 | V | PFI falling, STM70xS/T, VCC = 3.3 V | 24 |
| Operating voltage | VCC | 1.2 | 5.5 | V | VCC (min) = 1.0 V for TA = 0 °C to +85 °C | 24 | |
| VCC supply current | ICC | 35 | 50 | µA | VCC < 3.6 V | 24 | |
| VCC supply current | ICC | 40 | 60 | µA | VCC < 5.5 V | 24 | |
| Input leakage current (WDI) | ILI | -1 | 1 | µA | 0 V < VIN < VCC | 24 | |
| Input leakage current (PFI) | ILI | -25 | 2 | 25 | nA | 0 V < VIN < VCC | 24 |
| Input leakage current (MR) | ILI | 25 | 80 | 250 | µA | VRST (max.) < VCC < 3.6 V | 24 |
| Input leakage current (MR) | ILI | 75 | 125 | 300 | µA | 4.5 V < VCC < 5.5 V | 24 |
| Input high voltage (MR) | VIH | 2 | V | 4.5 V < VCC < 5.5 V | 24 | ||
| Input low voltage (MR) | VIL | 0.8 | V | 4.5 V < VCC < 5.5 V | 24 | ||
| Input low voltage (MR) | VIL | 0.6 | V | VRST (max.) < VCC < 3.6 V | 24 | ||
| Output low voltage (PFO, RST, RST, WDO) | VOL | 0.3 | V | VCC = VRST (max.), ISINK = 3.2 mA | 24 | ||
| Output low voltage (RST) | VOL | 0.3 | V | ISINK = 50 µA, VCC = 1.0 V, TA = 0 °C to 85 °C | 24 | ||
| Output high voltage (RST, RST, WDO) | VOH | 2.4 | V | ISOURCE = 1 mA, VCC = VRST (max.) | 24 | ||
| Storage temperature | TSTG | -55 | 150 | °C | VCC off | 21 | |
| Lead solder temperature | TSLD | 260 | °C | 10 seconds | 21 | ||
| Input or output voltage | VIO | -0.3 | V | Max is VCC + 0.3 V | 21 | ||
| Supply voltage | VCC | -0.3 | 7 | V | 21 | ||
| Output current | IO | 20 | mA | 21 | |||
| Power dissipation | PD | 320 | mW | 21 | |||
| VCC supply voltage (operating) | VCC | 1 | 5.5 | V | Operating and AC measurement conditions | 22 | |
| Ambient operating temperature | TA | -40 | 85 | °C | 22 |
CAD (KiCad official)
- Symbol:
STM706SM6F - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
stm706sm6f-etched.step/stm706sm6f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm706sm6f.step/stm706sm6f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (32 pp, sha256
fe2adb0e76018e05, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM706SM6F
**STMicroelectronics** · Monitors & Reset Circuits · SOIC-8
STM706SM6F from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low push-button reset input with internal 40 kΩ pull-up that asserts reset while low and for trec (140 to 280 ms) after it returns high; may be left open if unused. |
| 2 | VCC | power_in | Supply voltage input monitored against the reset threshold (STM706S: 2.85 to 3.00 V), with absolute maximum of 7.0 V and operating range up to 5.5 V. |
| 3 | VSS | power_in | Ground. |
| 4 | PFI | input | Power-fail comparator input that drives PFO low when below the VPFI threshold (1.25 V typ.); connect to ground if unused. |
| 5 | PFO | output | Push-pull power-fail output that goes low when PFI is below VPFI and stays high otherwise; leave open if unused and do not force it low from a processor. |
| 6 | WDI | input | Watchdog input where a high or low level lasting 1.6 s (typ.) without an edge triggers WDO, and the timer clears on any rising or falling edge or while reset is asserted. |
| 7 | RST | output | Active-low reset output that stays low whenever VCC is below the reset threshold or MR is low, and remains low for trec (200 ms typ.) afterwards. |
| 8 | WDO | output | Push-pull watchdog output that goes low when WDI has no transition within 1.6 s or when VCC falls below the reset threshold, and returns high on a WDI transition, MR low, or as soon as VCC exceeds the threshold. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reset threshold (VCC falling), STM70xS | VRST | 2.85 | 2.93 | 3 | V | For VCC falling | 25 |
| RST pulse width (blank option) | trec | 140 | 200 | 280 | ms | Blank (see Table 9) | 25 |
| Watchdog timeout period | tWD | 1.12 | 1.6 | 2.24 | s | STM70xS/70xT, VCC = 3.3 V | 25 |
| PFI input threshold | VPFI | 1.2 | 1.25 | 1.3 | V | PFI falling, STM70xS/T, VCC = 3.3 V | 24 |
| Operating voltage | VCC | 1.2 | | 5.5 | V | VCC (min) = 1.0 V for TA = 0 °C to +85 °C | 24 |
| VCC supply current | ICC | | 35 | 50 | µA | VCC < 3.6 V | 24 |
| VCC supply current | ICC | | 40 | 60 | µA | VCC < 5.5 V | 24 |
| Input leakage current (WDI) | ILI | -1 | | 1 | µA | 0 V < VIN < VCC | 24 |
| Input leakage current (PFI) | ILI | -25 | 2 | 25 | nA | 0 V < VIN < VCC | 24 |
| Input leakage current (MR) | ILI | 25 | 80 | 250 | µA | VRST (max.) < VCC < 3.6 V | 24 |
| Input leakage current (MR) | ILI | 75 | 125 | 300 | µA | 4.5 V < VCC < 5.5 V | 24 |
| Input high voltage (MR) | VIH | 2 | | | V | 4.5 V < VCC < 5.5 V | 24 |
| Input low voltage (MR) | VIL | | | 0.8 | V | 4.5 V < VCC < 5.5 V | 24 |
| Input low voltage (MR) | VIL | | | 0.6 | V | VRST (max.) < VCC < 3.6 V | 24 |
| Output low voltage (PFO, RST, RST, WDO) | VOL | | | 0.3 | V | VCC = VRST (max.), ISINK = 3.2 mA | 24 |
| Output low voltage (RST) | VOL | | | 0.3 | V | ISINK = 50 µA, VCC = 1.0 V, TA = 0 °C to 85 °C | 24 |
| Output high voltage (RST, RST, WDO) | VOH | 2.4 | | | V | ISOURCE = 1 mA, VCC = VRST (max.) | 24 |
| Storage temperature | TSTG | -55 | | 150 | °C | VCC off | 21 |
| Lead solder temperature | TSLD | | | 260 | °C | 10 seconds | 21 |
| Input or output voltage | VIO | -0.3 | | | V | Max is VCC + 0.3 V | 21 |
| Supply voltage | VCC | -0.3 | | 7 | V | | 21 |
| Output current | IO | | | 20 | mA | | 21 |
| Power dissipation | PD | | | 320 | mW | | 21 |
| VCC supply voltage (operating) | VCC | 1 | | 5.5 | V | Operating and AC measurement conditions | 22 |
| Ambient operating temperature | TA | -40 | | 85 | °C | | 22 |
## CAD (KiCad official)
- Symbol: `STM706SM6F`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `stm706sm6f-etched.step` / `stm706sm6f-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm706sm6f.step` / `stm706sm6f.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm706sm6f.pdf) (32 pp, sha256 `fe2adb0e76018e05`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm706sm6f-datasheet.pdf)