STM706RAM6F

STMicroelectronics · Supervisor And Reset ICs · SO-8

STM706RAM6F from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MR	input	Active-low push-button reset input with an internal 40 kΩ pull-up; reset stays asserted while MR is low and for trec after it returns high, and it may be left open, floated, or tied to VCC when unused.
2	VCC	power_in	Supply voltage monitored against the reset threshold VRST; the operating range is 1.0 to 5.5 V (Table 5) with an absolute maximum of 7.0 V.
3	VSS	power_in	Ground reference pin for the device.
4	PFI	input	Power-fail input compared to an internal 1.25 V (typ.) threshold VPFI; PFO goes low when PFI falls below VPFI, and PFI should be connected to VSS if the comparator is unused.
5	PFO	output	Push-pull power-fail output that goes low when PFI is below VPFI and must not be forced low by a processor; leave open if unused.
6	WDI	input	Watchdog input that must be toggled within tWD (1.6 s typ.) to prevent a WDO assertion, with transitions as short as 50 ns detected; the float-to-disable feature applies only to the 'D' version, which this part is not.
7	RST	output	Active-low push-pull reset output that is held low while VCC is below VRST or MR is low and for trec after release (160 to 280 ms, typ. 200 ms for the A suffix), guaranteed valid down to VCC = 1 V.
8	WDO	output	Push-pull watchdog output that goes low when WDI is not toggled within 1.6 s or when VCC falls below VRST, and returns high once VCC exceeds VRST; connect to MR to generate a reset on watchdog timeout.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SO-8
Category	Power Management (PMIC)
Pins	8

CAD (KiCad official)

Symbol: STM706RAM6F
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)
3D model files: stm706ram6f-etched.step / stm706ram6f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm706ram6f.step / stm706ram6f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (32 pp, sha256 fe2adb0e76018e05, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# STM706RAM6F

**STMicroelectronics** · Supervisor And Reset ICs · SO-8

STM706RAM6F from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low push-button reset input with an internal 40 kΩ pull-up; reset stays asserted while MR is low and for trec after it returns high, and it may be left open, floated, or tied to VCC when unused. |
| 2 | VCC | power_in | Supply voltage monitored against the reset threshold VRST; the operating range is 1.0 to 5.5 V (Table 5) with an absolute maximum of 7.0 V. |
| 3 | VSS | power_in | Ground reference pin for the device. |
| 4 | PFI | input | Power-fail input compared to an internal 1.25 V (typ.) threshold VPFI; PFO goes low when PFI falls below VPFI, and PFI should be connected to VSS if the comparator is unused. |
| 5 | PFO | output | Push-pull power-fail output that goes low when PFI is below VPFI and must not be forced low by a processor; leave open if unused. |
| 6 | WDI | input | Watchdog input that must be toggled within tWD (1.6 s typ.) to prevent a WDO assertion, with transitions as short as 50 ns detected; the float-to-disable feature applies only to the 'D' version, which this part is not. |
| 7 | RST | output | Active-low push-pull reset output that is held low while VCC is below VRST or MR is low and for trec after release (160 to 280 ms, typ. 200 ms for the A suffix), guaranteed valid down to VCC = 1 V. |
| 8 | WDO | output | Push-pull watchdog output that goes low when WDI is not toggled within 1.6 s or when VCC falls below VRST, and returns high once VCC exceeds VRST; connect to MR to generate a reset on watchdog timeout. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## CAD (KiCad official)

- Symbol: `STM706RAM6F`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `stm706ram6f-etched.step` / `stm706ram6f-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm706ram6f.step` / `stm706ram6f.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589831153806184448) (32 pp, sha256 `fe2adb0e76018e05`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm706ram6f-datasheet.pdf)