STM6905SFEDS6F from STMicroelectronics, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MR	input	Active-low manual reset input with an internal 10 kΩ pull-up to VCC, which can be driven from TTL/CMOS or open-drain logic or connected to VSS through a switch.
2	VCC	power_in	Primary supply voltage input (0.8 V to 5.5 V operating) and integrated fixed-threshold undervoltage monitor, with reset output valid for VCC ≥ 0.8 V.
3	V2IN	input	Second fixed-threshold reset monitor input; this SF variant has a factory-programmed VRST2 of 1.050 V (range 2.333 V to 1.050 V across variants).
4	VSS	power_in	Ground pin for the power supply.
5	V3IN	input	Adjustable reset comparator input with a 600 mV internal reference (VRSTIN 589 mV to 611 mV), where RST is asserted when the voltage at the pin falls below 600 mV; set by an external resistor divider.
6	V4IN	input	Adjustable reset comparator input with a 600 mV internal reference (VRSTIN 589 mV to 611 mV), where RST is asserted when the voltage at the pin falls below 600 mV; set by an external resistor divider.
7	V5IN	input	Adjustable reset comparator input with a 600 mV internal reference (VRSTIN 589 mV to 611 mV), where RST is asserted when the voltage at the pin falls below 600 mV; set by an external resistor divider.
8	RST	output	Active-low open-drain reset output with a 10 kΩ internal pull-up, asserted low when any monitored supply or MR falls below its threshold and kept low for tREC after all are back above threshold.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	MSOP-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCC reset threshold (falling), S suffix	VRST1	2.925	2.955	2.985	V	S (falling), 25 °C	12
VCC reset threshold (falling), S suffix	VRST1	2.902		3.008	V	S (falling), -40 °C to 85 °C	12
V2IN reset threshold (falling), F suffix	VRST2	1.04	1.05	1.061	V	F (falling), 25 °C	12
V2IN reset threshold (falling), F suffix	VRST2	1.031		1.069	V	F (falling), -40 °C to 85 °C	12
Operating voltage	VCC	0.8		5.5	V		12
VCC supply current	ICC		12	16	µA	VCC < 5.5 V	12
VCC supply current	ICC		11	15	µA	VCC = 3.3 V	12
V2IN supply current	I2IN		3	5	µA	V2IN = 3.3 V	12
Input leakage current (MR)	ILI	-0.5		0.5	µA	VIN = VCC or VSS	12
Open drain RST output leakage current	ILO	-0.5		0.5	µA	VCC > VRST, RST not asserted	12
Output low voltage (RST, open drain)	VOL			0.3	V	VCC ≥ 0.8 V, ISINK = 1 µA	12
Output low voltage (RST, open drain)	VOL			0.4	V	VCC ≥ 4.5 V, ISINK = 3.2 mA	12
Reset threshold hysteresis	VHYST		0.5		%	Referenced to VRST1/VRST2 typical	13
VCC to RST delay	tRD		20		µs	VCC = (VRST1 + 100 mV) to (VRST1, 100 mV)	13
RST time-out period, Option E	tREC	140	210	280	ms	Option E	13
V3IN, V4IN, V5IN input threshold	VRSTIN	589	600	611	mV		13
V3IN, V4IN, V5IN input current	IRSTIN	-25		25	nA	V3IN, V4IN, V5IN > 0.8 V	13
V3IN, V4IN, V5IN hysteresis			3		mV		13
V3IN, V4IN, V5IN to RST output delay	tRSTIND		22		µs	VRSTIN to (VRSTIN, 30 mV)	13
MR input voltage (low)	VIL			0.3	x VCC		13
MR input voltage (high)	VIH	0.7			x VCC		13
MR minimum pulse width	tMLMH	1			µs		13
MR to RST output delay	tMLRL		200		ns		13
MR glitch immunity			100		ns		13
MR pull-up resistance			10		kΩ		13
Ambient operating temperature	TA	-40		85	°C	Valid for ambient operating temperature	13
Storage temperature (VCC off)	TSTG	-55		150	°C	VCC off	11
Lead solder temperature for 10 seconds	TSLD			260	°C	10 seconds	11
Input or output voltage	VIO	-0.3			V	Max printed as VCC +0.3	11
Supply voltage	VCC	-0.3		7	V		11
Output current	IO			20	mA		11
Thermal resistance (junction to ambient)	θJA		146		°C/W		11

CAD (KiCad official)

Symbol: STM6905SFEDS6F
Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
3D model: MSOP-8 (KiCad packages3D, STEP)
3D model files: stm6905sfeds6f-etched.step / stm6905sfeds6f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm6905sfeds6f.step / stm6905sfeds6f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (19 pp, sha256 5c9c710bdeedb05f, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STM6905SFEDS6F

Verified STM6905SFEDS6F

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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