component
STM6821MWY6F
Public Made by Adomby adom
STMicroelectronics Supervisor And Reset ICs, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+8−5@@ -53,7 +53,7 @@ "number": "1", "name": "RST", "type": "output",- "description": "Active-high push-pull reset output (inverse of RST); asserted high whenever VCC falls below VRST (4.270-4.490 V for M-grade), watchdog timeout occurs, or MR is logic low; VOH \u2265 0.8 VCC with ISOURCE up to 800 \u00b5A (VCC \u2265 4.25 V); remains asserted for trec (140-280 ms, typ. 200 ms) after fault clears."+ "description": "Active-high push-pull reset output (inverse of RST); asserted high whenever VCC falls below VRST (4.270-4.490 V for M-grade), watchdog timeout occurs, or MR is logic low; VOH ≥ 0.8 VCC with ISOURCE up to 800 µA (VCC ≥ 4.25 V); remains asserted for trec (140-280 ms, typ. 200 ms) after fault clears." }, { "number": "2",@@ -65,19 +65,19 @@ "number": "3", "name": "MR", "type": "input",- "description": "Active-low manual/push-button reset input with internal 52 k\u03a9 (typ.) pull-up resistor; a logic low asserts the reset output and holds it for trec after MR returns high; VIL < 0.3 VCC (VRST < 4.0 V); minimum pulse width 1 \u00b5s; may be left open if unused."+ "description": "Active-low manual/push-button reset input with internal 52 kΩ (typ.) pull-up resistor; a logic low asserts the reset output and holds it for trec after MR returns high; VIL < 0.3 VCC (VRST < 4.0 V); minimum pulse width 1 µs; may be left open if unused." }, { "number": "4", "name": "WDI", "type": "input",- "description": "Watchdog input; if held static (high or low) for \u2265 tWD (typ. 1.6 s, range 1.12-2.24 s) the watchdog timer expires and reset is asserted; timer clears on any rising or falling edge or while reset is asserted; WDI = VCC draws up to 160 \u00b5A (time-average); float or tristate to disable watchdog (max leakage 10 \u00b5A, max load capacitance 200 pF)."+ "description": "Watchdog input; if held static (high or low) for ≥ tWD (typ. 1.6 s, range 1.12-2.24 s) the watchdog timer expires and reset is asserted; timer clears on any rising or falling edge or while reset is asserted; WDI = VCC draws up to 160 µA (time-average); float or tristate to disable watchdog (max leakage 10 µA, max load capacitance 200 pF)." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Supply voltage, 1.0 to 5.5 V operating range; quiescent ICC 4 \u00b5A typ. / 12 \u00b5A max (MR and WDI unconnected, VCC < 3.6 V); reset output guaranteed valid down to VCC = 1.0 V (TA = 0 to 85 \u00b0C)."+ "description": "Supply voltage, 1.0 to 5.5 V operating range; quiescent ICC 4 µA typ. / 12 µA max (MR and WDI unconnected, VCC < 3.6 V); reset output guaranteed valid down to VCC = 1.0 V (TA = 0 to 85 °C)." } ], "provenance": {@@ -155,5 +155,8 @@ "docs/stm6821mwy6f-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }