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STM32WB55CGU6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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STM32WB55CGU6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32WB55CGU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC, LSE and backup registers, specified from 1.55 to 3.6 V (VBAT backup operating voltage). |
| 2 | PC14-OSC32_IN | bidirectional | Supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz with a 30 pF load and it must not drive current sources; alternate function OSC32_IN for the LSE crystal. |
| 3 | PC15-OSC32_OUT | bidirectional | Supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz with a 30 pF load and it must not drive current sources; alternate function OSC32_OUT for the LSE crystal. |
| 4 | PH3-BOOT0 | bidirectional | 5 V-tolerant FT I/O multiplexed with the BOOT0 boot-mode function and with LSCO clock output (alternate function CM4_EVENTOUT, LSCO). |
| 5 | PB8 | bidirectional | 5 V-tolerant FT_fl I/O (Fm+ capable, LCD function supplied by VLCD) with alternate functions TIM1_CH2N, SAI1_PDM_CK1, I2C1_SCL, QUADSPI_BK1_IO1, LCD_SEG16, SAI1_MCLK_A and TIM16_CH1. |
| 6 | PB9 | bidirectional | 5 V-tolerant FT_fla I/O (Fm+ capable, LCD and analog switch functions) with alternate functions TIM1_CH3N, I2C1_SDA, SPI2_NSS, IR_OUT, QUADSPI_BK1_IO0 and TIM17_CH1. |
| 7 | NRST | bidirectional | Bidirectional reset pin with weak pull-up resistor (RST structure). |
| 8 | VDDA | power_in | Analog supply for the ADC, comparators and voltage reference buffer, 1.62 to 3.6 V when ADC or COMP is used; on UFQFPN48 it is connected to VREF+. |
| 9 | PA0 | bidirectional | 5 V-tolerant FT_a I/O with analog switch function supplied by VDDA; alternate functions include TIM2_CH1, COMP1_OUT, SAI1_EXTCLK and TIM2_ETR, and additional functions COMP1_INM, ADC1_IN5 and RTC_TAMP2/WKUP1. |
| 10 | PA1 | bidirectional | 5 V-tolerant FT_la I/O with analog switch function supplied by VDDA; alternate functions include TIM2_CH2, I2C1_SMBA, SPI1_SCK and LCD_SEG0, and additional functions COMP1_INP and ADC1_IN6. |
| 11 | PA2 | bidirectional | 5 V-tolerant FT_la I/O with analog switch function supplied by VDDA; alternate functions include LSCO clock output, TIM2_CH3, LPUART1_TX and QUADSPI_BK1_NCS, and additional functions COMP2_INM, ADC1_IN7 and WKUP4. |
| 12 | PA3 | bidirectional | 5 V-tolerant FT_la I/O with analog switch function supplied by VDDA; alternate functions include TIM2_CH4, SAI1_PDM_CK1, LPUART1_RX and QUADSPI_CLK, and additional functions COMP2_INP and ADC1_IN8. |
| 13 | PA4 | bidirectional | 5 V-tolerant FT_a I/O with analog switch function supplied by VDDA; alternate functions include SPI1_NSS, SAI1_FS_B and LPTIM2_OUT, and additional functions COMP1_INM, COMP2_INM and ADC1_IN9. |
| 14 | PA5 | bidirectional | 5 V-tolerant FT_a I/O with analog switch function supplied by VDDA; alternate functions include TIM2_CH1, TIM2_ETR, SPI1_SCK and LPTIM2_ETR, and additional functions COMP1_INM, COMP2_INM and ADC1_IN10. |
| 15 | PA6 | bidirectional | 5 V-tolerant FT_la I/O; alternate functions include TIM1_BKIN, SPI1_MISO, LPUART1_CTS, QUADSPI_BK1_IO3 and TIM16_CH1, and additional function ADC1_IN11. |
| 16 | PA7 | bidirectional | 5 V-tolerant FT_fla I/O (Fm+ capable, analog switch function supplied by VDDA); alternate functions include TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2 and TIM17_CH1, and additional function ADC1_IN12. |
| 17 | PA8 | bidirectional | 5 V-tolerant FT_la I/O; alternate functions include MCO clock output, TIM1_CH1, USART1_CK, SAI1_SCK_A and LPTIM2_OUT, and additional function ADC1_IN15. |
| 18 | PA9 | bidirectional | 5 V-tolerant FT_fla I/O (Fm+ capable, analog switch function supplied by VDDA); alternate functions include TIM1_CH2, I2C1_SCL, SPI2_SCK, USART1_TX and SAI1_FS_A, and additional functions COMP1_INM and ADC1_IN16. |
| 19 | PB2 | bidirectional | 5 V-tolerant FT_a I/O with analog switch function supplied by VDDA; alternate functions include RTC_OUT, LPTIM1_OUT, I2C3_SMBA, SPI1_NSS and SAI1_EXTCLK, and additional function COMP1_INP. |
| 20 | VDD | power_in | Standard operating voltage supply of 1.71 to 3.6 V for I/Os, the internal regulator and system functions. |
| 21 | RF1 | bidirectional | RF input/output that must be connected to the antenna through a low-pass matching network, and that uses the nominal PCB layout. |
| 22 | VSSRF | power_in | RF ground that must be connected to GND. |
| 23 | VDDRF | power_in | Dedicated RF supply that must be connected to VDD, with minimum RF voltage of 1.71 V. |
| 24 | OSC_OUT | output | 32 MHz main oscillator output, also used as HSE source; use the nominal PCB layout according to the reference design (AN5165). |
| 25 | OSC_IN | input | 32 MHz main oscillator input, also used as HSE source; use the nominal PCB layout according to the reference design (AN5165). |
| 26 | AT0 | output | Reserved pin that must be kept unconnected. |
| 27 | AT1 | output | Reserved pin that must be kept unconnected. |
| 28 | PB0 | bidirectional | 3.6 V-tolerant TT I/O with alternate functions COMP1_OUT, CM4_EVENTOUT and RF_TX_MOD_EXT_PA; injected current limited to -5/0 mA and high output frequency may impact RF performance. |
| 29 | PB1 | bidirectional | 3.6 V-tolerant TT I/O with alternate functions LPUART1_RTS_DE, LPTIM2_IN1 and CM4_EVENTOUT; injected current limited to -5/0 mA and high output frequency may impact RF performance. |
| 30 | PE4 | bidirectional | 5 V-tolerant FT I/O with alternate function CM4_EVENTOUT. |
| 31 | VFBSMPS | power_in | SMPS feedback voltage input, 1.4 to 3.6 V. |
| 32 | VSSSMPS | power_in | Ground for the SMPS step-down converter that must be connected to GND. |
| 33 | VLXSMPS | power_out | SMPS switching node connected to the external inductor L1 (2.2 uH for 8 MHz or 10 uH for 4 MHz operation). |
| 34 | VDDSMPS | power_in | SMPS supply that must always be connected to VDD, from 1.71 to 3.6 V. |
| 35 | VDD | power_in | Standard operating voltage supply of 1.71 to 3.6 V for I/Os, the internal regulator and system functions. |
| 36 | PA10 | bidirectional | 5 V-tolerant FT_fl I/O (Fm+ capable, LCD function supplied by VLCD); alternate functions include TIM1_CH3, I2C1_SDA, USART1_RX, USB_CRS_SYNC and SAI1_SD_A. |
| 37 | PA11 | bidirectional | 5 V-tolerant FT_u I/O with USB function supplied by VDDB, alternate functions TIM1_CH4, SPI1_MISO, USART1_CTS and USB_DM. |
| 38 | PA12 | bidirectional | 5 V-tolerant FT_u I/O with USB function supplied by VDDUSB; alternate functions include TIM1_ETR, SPI1_MOSI, LPUART1_RX, USART1_RTS_DE and USB_DP. |
| 39 | PA13 | bidirectional | 5 V-tolerant FT_u I/O that after reset is configured as the JTMS-SWDIO debug function, with internal pull-up activated. |
| 40 | VDDUSB | power_in | USB transceiver supply of 3.0 to 3.6 V when USB is used; must be connected to VDD when not used. |
| 41 | PA14 | bidirectional | 5 V-tolerant FT_l I/O that after reset is configured as the JTCK-SWCLK debug function, with internal pull-down activated. |
| 42 | PA15 (JTDI) | bidirectional | 5 V-tolerant FT_l I/O that after reset is configured as the JTDI debug function, with internal pull-up activated; alternate functions include TIM2_CH1, SPI1_NSS and MCO. |
| 43 | PB3 (JTDO) | bidirectional | 5 V-tolerant FT_la I/O with analog switch function supplied by VDDA; alternate functions include JTDO-TRACESWO, TIM2_CH2, SPI1_SCK and USART1_RTS_DE, and additional function COMP2_INM. |
| 44 | PB4 (NJTRST) | bidirectional | 5 V-tolerant FT_fla I/O that after reset is configured as the NJTRST debug function, with internal pull-up activated; alternate functions include I2C3_SDA, SPI1_MISO and USART1_CTS. |
| 45 | PB5 | bidirectional | 5 V-tolerant FT_l I/O (LCD function supplied by VLCD); alternate functions include LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK and LPUART1_TX. |
| 46 | PB6 | bidirectional | 5 V-tolerant FT_fla I/O (Fm+ capable, analog switch function supplied by VDDA); alternate functions include LPTIM1_ETR, I2C1_SCL, USART1_TX and MCO, and additional function COMP2_INP. |
| 47 | PB7 | bidirectional | 5 V-tolerant FT_fla I/O (Fm+ capable, analog switch function supplied by VDDA); alternate functions include LPTIM1_IN2, TIM1_BKIN, I2C1_SDA and USART1_RX, and additional functions COMP2_INM and PVD_IN. |
| 48 | VDD | power_in | Standard operating voltage supply of 1.71 to 3.6 V for I/Os, the internal regulator and system functions. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage | VDDX - VSS | -0.3 | 4 | V | Including VDD, VDDA, VDDUSB, VLCD, VDDRF, VDDSMPS, VBAT, VREF+ | 85 | |
| Input voltage on TT_xx pins | VIN | 4 | V | Input voltage on TT_xx pins | 85 | ||
| Input voltage on any other pin | VIN | 4 | V | Input voltage on any other pin | 85 | ||
| Variations between different VDDX power pins | /ΔVDDx/ | 50 | mV | Variations between different VDDX power pins of the same domain | 85 | ||
| Variations between all the different ground pins | /VSSx-VSS/ | 50 | mV | Variations between all ground pins, include VREF- | 85 | ||
| Allowed voltage difference for VREF+ > VDDA | VREF+ - VDDA | 0.4 | V | VREF+ > VDDA | 85 | ||
| Total current into sum of all VDD power lines (source) | ∑IVDD | 130 | mA | 85 | |||
| Total current out of sum of all VSS ground lines (sink) | ∑IVSS | 130 | mA | 85 | |||
| Maximum current into each VDD power pin (source) | IVDD(PIN) | 100 | mA | 85 | |||
| Maximum current out of each VSS ground pin (sink) | IVSS(PIN) | 100 | mA | 85 | |||
| Output current sunk by any I/O and control pin except FT_f | IIO(PIN) | 20 | mA | Sunk, any I/O and control pin except FT_f | 85 | ||
| Output current sunk by any FT_f pin | IIO(PIN) | 20 | mA | Sunk, any FT_f pin | 85 | ||
| Output current sourced by any I/O and control pin | IIO(PIN) | 20 | mA | Sourced, any I/O and control pin | 85 | ||
| Total output current sunk by sum of all I/Os and control pins | ∑IIO(PIN) | 100 | mA | Sunk, sum of all I/Os and control pins | 85 | ||
| Total output current sourced by sum of all I/Os and control pins | ∑IIO(PIN) | 100 | mA | Sourced, sum of all I/Os and control pins | 85 | ||
| Injected current on FT_xxx, TT_xx, RST and B pins | IINJ(PIN) | -5 | 0 | mA | Except PB0 and PB1 | 85 | |
| Injected current on PB0 and PB1 | IINJ(PIN) | -5 | 0 | mA | PB0 and PB1 | 85 | |
| Total injected current (sum of all I/Os and control pins) | ∑/IINJ(PIN)/ | 25 | mA | Sum of all I/Os and control pins | 85 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 86 | ||
| Maximum junction temperature | TJ | 130 | °C | 86 | |||
| Internal AHB clock frequency | fHCLK | 0 | 64 | MHz | 87 | ||
| Internal APB1 clock frequency | fPCLK1 | 0 | 64 | MHz | 87 | ||
| Internal APB2 clock frequency | fPCLK2 | 0 | 64 | MHz | 87 | ||
| Standard operating voltage | VDD | 1.71 | 3.6 | V | Standard operating voltage | 87 | |
| Analog supply voltage | VDDA | 1.62 | 3.6 | V | ADC or COMP used | 87 | |
| Analog supply voltage | VDDA | 2.4 | 3.6 | V | VREFBUF used | 87 | |
| Analog supply voltage | VDDA | 0 | V | ADC, COMP, VREFBUF not used | 87 | ||
| Backup operating voltage | VBAT | 1.55 | 3.6 | V | 87 | ||
| SMPS feedback voltage | VFBSMPS | 1.4 | 3.6 | V | 88 | ||
| Minimum RF voltage | VDDRF | 1.71 | 3.6 | V | 88 | ||
| USB supply voltage | VDDUSB | 3 | 3.6 | V | USB used | 88 | |
| USB supply voltage | VDDUSB | 0 | 3.6 | V | USB not used | 88 | |
| I/O input voltage | VIN | -0.3 | V | TT_xx I/O; max VDD + 0.3 | 88 | ||
| Power dissipation UFQFPN48 | PD | 803 | mW | TA = 85 °C for suffix 6 | 88 | ||
| Ambient temperature for the suffix 6 version | TA | -40 | 85 | °C | Maximum power dissipation | 88 | |
| Ambient temperature for the suffix 6 version | TA | 105 | °C | Low-power dissipation | 88 | ||
| Junction temperature range | TJ | -40 | 105 | °C | Suffix 6 version | 88 | |
| Frequency operating range (BLE) | Fop | 2402 | 2480 | MHz | 88 | ||
| Frequency operating range (802.15.4) | Fop | 2405 | 2480 | MHz | 93 | ||
| Internal reference voltage | VREFINT | 1.182 | 1.212 | 1.232 | V | -40 °C < TA < +125 °C | 98 |
| Internal reference voltage spread over the temperature range | ΔVREFINT | 5 | 7.5 | mV | VDD = 3 V | 98 | |
| Temperature coefficient | TCoeff | 30 | 50 | ppm/°C | -40 °C < TA < +125 °C | 98 | |
| Long term stability | ACoeff | 300 | 1000 | ppm | 1000 hours, T = 25 °C | 98 | |
| Voltage coefficient | VDDCoeff | 250 | 1200 | ppm/V | 3.0 V < VDD < 3.6 V | 98 | |
| 1/4 reference voltage | VREFINT_DIV1 | 24 | 25 | 26 | % | % of VREFINT | 98 |
| 1/2 reference voltage | VREFINT_DIV2 | 49 | 50 | 51 | % | % of VREFINT | 98 |
| 3/4 reference voltage | VREFINT_DIV3 | 74 | 75 | 76 | % | % of VREFINT | 98 |
| Brown-out reset threshold 0 (rising edge) | VBOR0 | 1.62 | 1.66 | 1.7 | V | Rising edge | 96 |
| Brown-out reset threshold 0 (falling edge) | VBOR0 | 1.6 | 1.64 | 1.69 | V | Falling edge | 96 |
| Brown-out reset threshold 1 (rising edge) | VBOR1 | 2.06 | 2.1 | 2.14 | V | Rising edge | 96 |
| Brown-out reset threshold 1 (falling edge) | VBOR1 | 1.96 | 2 | 2.04 | V | Falling edge | 96 |
| Brown-out reset threshold 2 (rising edge) | VBOR2 | 2.26 | 2.31 | 2.35 | V | Rising edge | 96 |
| Brown-out reset threshold 2 (falling edge) | VBOR2 | 2.16 | 2.2 | 2.24 | V | Falling edge | 96 |
| Brown-out reset threshold 3 (rising edge) | VBOR3 | 2.56 | 2.61 | 2.66 | V | Rising edge | 96 |
| Brown-out reset threshold 3 (falling edge) | VBOR3 | 2.47 | 2.52 | 2.57 | V | Falling edge | 96 |
| Supply current in Stop 2 mode, RTC disabled | IDD(Stop 2) | 1.85 | 4.17 | µA | VDD = 3.0 V, TA = 25 °C, LCD disabled, BLE disabled | 105 |
CAD (KiCad official)
- Symbol:
STM32WB55CGU6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32wb55cgu6-etched.step/stm32wb55cgu6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32wb55cgu6.step/stm32wb55cgu6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (193 pp, sha256
7eddf71700b00f75, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).