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STM32WB55CEU6
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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
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STM32WB55CEU6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32WB55CEU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC, LSE and backup registers, powered from a battery or supercapacitor or from VDD when neither is present, with a backup operating voltage of 1.55 to 3.6 V. |
| 2 | PC14-OSC32_IN | bidirectional | 5 V-tolerant FT I/O fed through the power switch, which sinks at most 3 mA, so output speed must not exceed 2 MHz at a 30 pF maximum load and the pin must not drive current sources; alternate function is OSC32_IN (LSE input). |
| 3 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant FT I/O fed through the power switch, which sinks at most 3 mA, so output speed must not exceed 2 MHz at a 30 pF maximum load and the pin must not drive current sources; alternate function is OSC32_OUT (LSE output). |
| 4 | PH3-BOOT0 | bidirectional | 5 V-tolerant FT I/O that carries the BOOT0 function and can also output the LSCO low-speed clock, which is available in Run and Stop modes. |
| 5 | PB8 | bidirectional | 5 V-tolerant FT_fl I/O that is Fm+ capable with 20 mA output drive and has its LCD function supplied by VLCD; alternate functions include I2C1_SCL, TIM1_CH2N, QUADSPI_BK1_IO1 and LCD_SEG16. |
| 6 | PB9 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with 20 mA output drive, has LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include I2C1_SDA, SPI2_NSS, IR_OUT, QUADSPI_BK1_IO0 and TIM17_CH1. |
| 7 | NRST | bidirectional | Bidirectional reset pin with a weak pull-up resistor; the internal reset pull-up is deactivated when the reset source is internal. |
| 8 | VDDA | power_in | Analog supply for the ADC, comparators and voltage reference buffer, specified at 1.62 to 3.6 V for ADC/COMP and at 2.4 V minimum when VREFBUF is used; on UFQFPN48 it is internally connected to VREF+ and must be connected to VDD when unused. |
| 9 | PA0 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include TIM2_CH1, COMP1_OUT, SAI1_EXTCLK and TIM2_ETR, and additional functions are COMP1_INM, ADC1_IN5 and RTC_TAMP2/WKUP1. |
| 10 | PA1 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include TIM2_CH2, I2C1_SMBA, SPI1_SCK and LCD_SEG0, and additional functions are COMP1_INP and ADC1_IN6. |
| 11 | PA2 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include LSCO, TIM2_CH3, LPUART1_TX, QUADSPI_BK1_NCS and COMP2_OUT, and additional functions are COMP2_INM, ADC1_IN7 and WKUP4; LSCO on this pin is available in Standby and Shutdown modes. |
| 12 | PA3 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include TIM2_CH4, SAI1_PDM_CK1, LPUART1_RX, QUADSPI_CLK and SAI1_MCLK_A, and additional functions are COMP2_INP and ADC1_IN8. |
| 13 | PA4 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include SPI1_NSS, SAI1_FS_B, LPTIM2_OUT and LCD_SEG5, and additional functions are COMP1_INM, COMP2_INM and ADC1_IN9. |
| 14 | PA5 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR and SAI1_SD_B, and additional functions are COMP1_INM, COMP2_INM and ADC1_IN10. |
| 15 | PA6 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include TIM1_BKIN, SPI1_MISO, LPUART1_CTS, QUADSPI_BK1_IO3, LCD_SEG3 and TIM16_CH1, and an additional function is ADC1_IN11. |
| 16 | PA7 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, COMP2_OUT and TIM17_CH1, and an additional function is ADC1_IN12. |
| 17 | PA8 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include MCO, TIM1_CH1, SAI1_PDM_CK2, USART1_CK, LCD_COM0 and LPTIM2_OUT, and an additional function is ADC1_IN15. |
| 18 | PA9 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include TIM1_CH2, SAI1_PDM_DI2, I2C1_SCL, SPI2_SCK, USART1_TX, LCD_COM1 and SAI1_FS_A, and additional functions are COMP1_INM and ADC1_IN16. |
| 19 | PB2 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include RTC_OUT, LPTIM1_OUT, I2C3_SMBA, SPI1_NSS, LCD_VLCD and SAI1_EXTCLK, and an additional function is COMP1_INP. |
| 20 | VDD | power_in | Main supply pin for the I/Os, internal regulator and system functions (RF, SMPS, reset, power management, internal clocks), specified at 1.71 to 3.6 V; VDD, VDDRF and VDDSMPS must be wired together. |
| 21 | RF1 | bidirectional | RF input/output that must be connected to the antenna through a low-pass matching network, using the nominal PCB layout. |
| 22 | VSSRF | power_in | RF ground pin that must be connected to GND, and the exposed pad must be connected to the GND plane for correct RF operation. |
| 23 | VDDRF | power_in | Dedicated RF supply that must be connected to VDD, with a minimum RF voltage of 1.71 V and maximum of 3.6 V. |
| 24 | OSC_OUT | output | Output of the 32 MHz main oscillator, also used as the HSE source, to be laid out per the nominal reference design (AN5165). |
| 25 | OSC_IN | input | Input of the 32 MHz main oscillator, also used as the HSE source, to be laid out per the nominal reference design (AN5165). |
| 26 | AT0 | output | Reserved pin that must be kept unconnected. |
| 27 | AT1 | output | Reserved pin that must be kept unconnected. |
| 28 | PB0 | bidirectional | 3.6 V-tolerant TT I/O with alternate functions COMP1_OUT and RF_TX_MOD_EXT_PA (external PA transmit control); output speed should be set to 00 during RF operation because frequencies above 32 kHz may affect RF performance, and injected current is limited to -5/0 mA. |
| 29 | PB1 | bidirectional | 3.6 V-tolerant TT I/O with alternate functions LPUART1_RTS_DE and LPTIM2_IN1; output speed should be set to 00 during RF operation because frequencies above 32 kHz may affect RF performance, and injected current is limited to -5/0 mA. |
| 30 | PE4 | bidirectional | 5 V-tolerant FT I/O with CM4_EVENTOUT as its only listed alternate function. |
| 31 | VFBSMPS | power_in | SMPS feedback voltage input, specified at 1.4 to 3.6 V. |
| 32 | VSSSMPS | power_in | Ground pin for the SMPS step-down converter. |
| 33 | VLXSMPS | power_out | SMPS switching node that connects to the step-down inductor L1 (2.2 µH for 8 MHz or 10 µH for 4 MHz operation per Table 6). |
| 34 | VDDSMPS | power_in | SMPS power input that must always be connected to VDD, wired together with VDD and VDDRF. |
| 35 | VDD | power_in | Main supply pin for the I/Os, internal regulator and system functions, specified at 1.71 to 3.6 V. |
| 36 | PA10 | bidirectional | 5 V-tolerant FT_fl I/O that is Fm+ capable with LCD function supplied by VLCD; alternate functions include TIM1_CH3, SAI1_PDM_DI1, I2C1_SDA, USART1_RX, USB_CRS_SYNC, LCD_COM2 and TIM17_BKIN. |
| 37 | PA11 | bidirectional | 5 V-tolerant FT_u I/O whose USB function (USB_DM) is supplied by VDDUSB when the USB alternate function is selected; other alternate functions include TIM1_CH4, TIM1_BKIN2, SPI1_MISO and USART1_CTS. |
| 38 | PA12 | bidirectional | 5 V-tolerant FT_u I/O whose USB function (USB_DP) is supplied by VDDUSB when the USB alternate function is selected; other alternate functions include TIM1_ETR, SPI1_MOSI, LPUART1_RX and USART1_RTS_DE. |
| 39 | PA13 | bidirectional | 5 V-tolerant FT_u I/O that after reset is configured as the JTMS-SWDIO debug function with its internal pull-up activated; other alternate functions include IR_OUT, USB_NOE and SAI1_SD_B. |
| 40 | VDDUSB | power_in | Independent USB transceiver supply that must be 3.0 to 3.6 V when USB is used, or connected to VDD or ground when USB is not used. |
| 41 | PA14 | bidirectional | 5 V-tolerant FT_l I/O with LCD function supplied by VLCD that after reset is configured as the JTCK-SWCLK debug function with its internal pull-down activated; other alternate functions include LPTIM1_OUT, I2C1_SMBA and SAI1_FS_B. |
| 42 | PA15 (JTDI) | bidirectional | 5 V-tolerant FT_l I/O with LCD function supplied by VLCD that after reset is configured as the JTDI debug function with its internal pull-up activated; other alternate functions include TIM2_CH1, TIM2_ETR, SPI1_NSS, TSC_G3_IO1 and MCO. |
| 43 | PB3 (JTDO) | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA that after reset is configured as the JTDO-TRACESWO debug function; other alternate functions include TIM2_CH2, SPI1_SCK, USART1_RTS_DE and SAI1_SCK_B, and an additional function is COMP2_INM. |
| 44 | PB4 (NJTRST) | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions and that after reset is configured as the NJTRST debug function with its internal pull-up activated; other alternate functions include I2C3_SDA, SPI1_MISO, USART1_CTS and TIM17_BKIN, and an additional function is COMP2_INP. |
| 45 | PB5 | bidirectional | 5 V-tolerant FT_l I/O with LCD function supplied by VLCD; alternate functions include LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, LPUART1_TX, LCD_SEG9, COMP2_OUT and TIM16_BKIN. |
| 46 | PB6 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include LPTIM1_ETR, I2C1_SCL, USART1_TX, LCD_SEG6, SAI1_FS_B, TIM16_CH1N and MCO, and an additional function is COMP2_INP. |
| 47 | PB7 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, LCD_SEG21 and TIM17_CH1N, and additional functions are COMP2_INM and PVD_IN. |
| 48 | VDD | power_in | Main supply pin for the I/Os, internal regulator and system functions, specified at 1.71 to 3.6 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32WB55CEU6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32wb55ceu6-etched.step/stm32wb55ceu6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32wb55ceu6.step/stm32wb55ceu6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (196 pp, sha256
c25acc0a128f2941, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM32WB55CEU6
**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32WB55CEU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC, LSE and backup registers, powered from a battery or supercapacitor or from VDD when neither is present, with a backup operating voltage of 1.55 to 3.6 V. |
| 2 | PC14-OSC32_IN | bidirectional | 5 V-tolerant FT I/O fed through the power switch, which sinks at most 3 mA, so output speed must not exceed 2 MHz at a 30 pF maximum load and the pin must not drive current sources; alternate function is OSC32_IN (LSE input). |
| 3 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant FT I/O fed through the power switch, which sinks at most 3 mA, so output speed must not exceed 2 MHz at a 30 pF maximum load and the pin must not drive current sources; alternate function is OSC32_OUT (LSE output). |
| 4 | PH3-BOOT0 | bidirectional | 5 V-tolerant FT I/O that carries the BOOT0 function and can also output the LSCO low-speed clock, which is available in Run and Stop modes. |
| 5 | PB8 | bidirectional | 5 V-tolerant FT_fl I/O that is Fm+ capable with 20 mA output drive and has its LCD function supplied by VLCD; alternate functions include I2C1_SCL, TIM1_CH2N, QUADSPI_BK1_IO1 and LCD_SEG16. |
| 6 | PB9 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with 20 mA output drive, has LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include I2C1_SDA, SPI2_NSS, IR_OUT, QUADSPI_BK1_IO0 and TIM17_CH1. |
| 7 | NRST | bidirectional | Bidirectional reset pin with a weak pull-up resistor; the internal reset pull-up is deactivated when the reset source is internal. |
| 8 | VDDA | power_in | Analog supply for the ADC, comparators and voltage reference buffer, specified at 1.62 to 3.6 V for ADC/COMP and at 2.4 V minimum when VREFBUF is used; on UFQFPN48 it is internally connected to VREF+ and must be connected to VDD when unused. |
| 9 | PA0 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include TIM2_CH1, COMP1_OUT, SAI1_EXTCLK and TIM2_ETR, and additional functions are COMP1_INM, ADC1_IN5 and RTC_TAMP2/WKUP1. |
| 10 | PA1 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include TIM2_CH2, I2C1_SMBA, SPI1_SCK and LCD_SEG0, and additional functions are COMP1_INP and ADC1_IN6. |
| 11 | PA2 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include LSCO, TIM2_CH3, LPUART1_TX, QUADSPI_BK1_NCS and COMP2_OUT, and additional functions are COMP2_INM, ADC1_IN7 and WKUP4; LSCO on this pin is available in Standby and Shutdown modes. |
| 12 | PA3 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include TIM2_CH4, SAI1_PDM_CK1, LPUART1_RX, QUADSPI_CLK and SAI1_MCLK_A, and additional functions are COMP2_INP and ADC1_IN8. |
| 13 | PA4 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include SPI1_NSS, SAI1_FS_B, LPTIM2_OUT and LCD_SEG5, and additional functions are COMP1_INM, COMP2_INM and ADC1_IN9. |
| 14 | PA5 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR and SAI1_SD_B, and additional functions are COMP1_INM, COMP2_INM and ADC1_IN10. |
| 15 | PA6 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include TIM1_BKIN, SPI1_MISO, LPUART1_CTS, QUADSPI_BK1_IO3, LCD_SEG3 and TIM16_CH1, and an additional function is ADC1_IN11. |
| 16 | PA7 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, COMP2_OUT and TIM17_CH1, and an additional function is ADC1_IN12. |
| 17 | PA8 | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA; alternate functions include MCO, TIM1_CH1, SAI1_PDM_CK2, USART1_CK, LCD_COM0 and LPTIM2_OUT, and an additional function is ADC1_IN15. |
| 18 | PA9 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include TIM1_CH2, SAI1_PDM_DI2, I2C1_SCL, SPI2_SCK, USART1_TX, LCD_COM1 and SAI1_FS_A, and additional functions are COMP1_INM and ADC1_IN16. |
| 19 | PB2 | bidirectional | 5 V-tolerant FT_a I/O with analog-switch function supplied by VDDA; alternate functions include RTC_OUT, LPTIM1_OUT, I2C3_SMBA, SPI1_NSS, LCD_VLCD and SAI1_EXTCLK, and an additional function is COMP1_INP. |
| 20 | VDD | power_in | Main supply pin for the I/Os, internal regulator and system functions (RF, SMPS, reset, power management, internal clocks), specified at 1.71 to 3.6 V; VDD, VDDRF and VDDSMPS must be wired together. |
| 21 | RF1 | bidirectional | RF input/output that must be connected to the antenna through a low-pass matching network, using the nominal PCB layout. |
| 22 | VSSRF | power_in | RF ground pin that must be connected to GND, and the exposed pad must be connected to the GND plane for correct RF operation. |
| 23 | VDDRF | power_in | Dedicated RF supply that must be connected to VDD, with a minimum RF voltage of 1.71 V and maximum of 3.6 V. |
| 24 | OSC_OUT | output | Output of the 32 MHz main oscillator, also used as the HSE source, to be laid out per the nominal reference design (AN5165). |
| 25 | OSC_IN | input | Input of the 32 MHz main oscillator, also used as the HSE source, to be laid out per the nominal reference design (AN5165). |
| 26 | AT0 | output | Reserved pin that must be kept unconnected. |
| 27 | AT1 | output | Reserved pin that must be kept unconnected. |
| 28 | PB0 | bidirectional | 3.6 V-tolerant TT I/O with alternate functions COMP1_OUT and RF_TX_MOD_EXT_PA (external PA transmit control); output speed should be set to 00 during RF operation because frequencies above 32 kHz may affect RF performance, and injected current is limited to -5/0 mA. |
| 29 | PB1 | bidirectional | 3.6 V-tolerant TT I/O with alternate functions LPUART1_RTS_DE and LPTIM2_IN1; output speed should be set to 00 during RF operation because frequencies above 32 kHz may affect RF performance, and injected current is limited to -5/0 mA. |
| 30 | PE4 | bidirectional | 5 V-tolerant FT I/O with CM4_EVENTOUT as its only listed alternate function. |
| 31 | VFBSMPS | power_in | SMPS feedback voltage input, specified at 1.4 to 3.6 V. |
| 32 | VSSSMPS | power_in | Ground pin for the SMPS step-down converter. |
| 33 | VLXSMPS | power_out | SMPS switching node that connects to the step-down inductor L1 (2.2 µH for 8 MHz or 10 µH for 4 MHz operation per Table 6). |
| 34 | VDDSMPS | power_in | SMPS power input that must always be connected to VDD, wired together with VDD and VDDRF. |
| 35 | VDD | power_in | Main supply pin for the I/Os, internal regulator and system functions, specified at 1.71 to 3.6 V. |
| 36 | PA10 | bidirectional | 5 V-tolerant FT_fl I/O that is Fm+ capable with LCD function supplied by VLCD; alternate functions include TIM1_CH3, SAI1_PDM_DI1, I2C1_SDA, USART1_RX, USB_CRS_SYNC, LCD_COM2 and TIM17_BKIN. |
| 37 | PA11 | bidirectional | 5 V-tolerant FT_u I/O whose USB function (USB_DM) is supplied by VDDUSB when the USB alternate function is selected; other alternate functions include TIM1_CH4, TIM1_BKIN2, SPI1_MISO and USART1_CTS. |
| 38 | PA12 | bidirectional | 5 V-tolerant FT_u I/O whose USB function (USB_DP) is supplied by VDDUSB when the USB alternate function is selected; other alternate functions include TIM1_ETR, SPI1_MOSI, LPUART1_RX and USART1_RTS_DE. |
| 39 | PA13 | bidirectional | 5 V-tolerant FT_u I/O that after reset is configured as the JTMS-SWDIO debug function with its internal pull-up activated; other alternate functions include IR_OUT, USB_NOE and SAI1_SD_B. |
| 40 | VDDUSB | power_in | Independent USB transceiver supply that must be 3.0 to 3.6 V when USB is used, or connected to VDD or ground when USB is not used. |
| 41 | PA14 | bidirectional | 5 V-tolerant FT_l I/O with LCD function supplied by VLCD that after reset is configured as the JTCK-SWCLK debug function with its internal pull-down activated; other alternate functions include LPTIM1_OUT, I2C1_SMBA and SAI1_FS_B. |
| 42 | PA15 (JTDI) | bidirectional | 5 V-tolerant FT_l I/O with LCD function supplied by VLCD that after reset is configured as the JTDI debug function with its internal pull-up activated; other alternate functions include TIM2_CH1, TIM2_ETR, SPI1_NSS, TSC_G3_IO1 and MCO. |
| 43 | PB3 (JTDO) | bidirectional | 5 V-tolerant FT_la I/O with LCD function supplied by VLCD and analog-switch function supplied by VDDA that after reset is configured as the JTDO-TRACESWO debug function; other alternate functions include TIM2_CH2, SPI1_SCK, USART1_RTS_DE and SAI1_SCK_B, and an additional function is COMP2_INM. |
| 44 | PB4 (NJTRST) | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions and that after reset is configured as the NJTRST debug function with its internal pull-up activated; other alternate functions include I2C3_SDA, SPI1_MISO, USART1_CTS and TIM17_BKIN, and an additional function is COMP2_INP. |
| 45 | PB5 | bidirectional | 5 V-tolerant FT_l I/O with LCD function supplied by VLCD; alternate functions include LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, LPUART1_TX, LCD_SEG9, COMP2_OUT and TIM16_BKIN. |
| 46 | PB6 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include LPTIM1_ETR, I2C1_SCL, USART1_TX, LCD_SEG6, SAI1_FS_B, TIM16_CH1N and MCO, and an additional function is COMP2_INP. |
| 47 | PB7 | bidirectional | 5 V-tolerant FT_fla I/O that is Fm+ capable with LCD and analog-switch functions; alternate functions include LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, LCD_SEG21 and TIM17_CH1N, and additional functions are COMP2_INM and PVD_IN. |
| 48 | VDD | power_in | Main supply pin for the I/Os, internal regulator and system functions, specified at 1.71 to 3.6 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `STM32WB55CEU6`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm32wb55ceu6-etched.step` / `stm32wb55ceu6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32wb55ceu6.step` / `stm32wb55ceu6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886723929509888) (196 pp, sha256 `c25acc0a128f2941`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm32wb55ceu6-datasheet.pdf)