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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32WB50CGU5

STMicroelectronics · RF Transceiver ICs · UFQFPN-48(7x7)

STM32WB50CGU5 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Battery backup supply voltage for RTC, LSE and backup registers, 1.55 to 3.6 V.
2	PC14-OSC32_IN	bidirectional	Port C GPIO 14 or 32.768 kHz low-speed external oscillator input, 5 V tolerant.
3	PC15-OSC32_OUT	bidirectional	Port C GPIO 15 or 32.768 kHz low-speed external oscillator output, 5 V tolerant.
4	PH3-BOOT0	bidirectional	Port H GPIO 3 or BOOT0 boot mode selection pin, 5 V tolerant.
5	PB8	bidirectional	Port B GPIO 8, 5 V tolerant Fm+ capable with alternate functions TIM1_CH2N, I2C1_SCL, TIM16_CH1.
6	PB9	bidirectional	Port B GPIO 9, 5 V tolerant with analog switch and alternate functions TIM1_CH3N, I2C1_SDA, IR_OUT, TIM17_CH1.
7	NRST	bidirectional	Bidirectional reset pin with weak internal pull-up resistor.
8	VDDA	power_in	Analog power supply for ADC connected to VREF+, 2.0 to 3.6 V.
9	PA0	bidirectional	Port A GPIO 0, 5 V tolerant with analog switch, with alternate functions TIM2_CH1, TIM2_ETR and additional functions ADC1_IN5, RTC_TAMP2/WKUP1.
10	PA1	bidirectional	Port A GPIO 1, 5 V tolerant with analog switch, with alternate functions TIM2_CH2, I2C1_SMBA, SPI1_SCK and additional function ADC1_IN6.
11	PA2	bidirectional	Port A GPIO 2, 5 V tolerant with analog switch, with alternate functions LSCO, TIM2_CH3 and additional functions ADC1_IN7, WKUP4.
12	PA3	bidirectional	Port A GPIO 3, 5 V tolerant with analog switch, with alternate function TIM2_CH4 and additional function ADC1_IN8.
13	PA4	bidirectional	Port A GPIO 4, 5 V tolerant with analog switch, with alternate functions SPI1_NSS, LPTIM2_OUT and additional function ADC1_IN9.
14	PA5	bidirectional	Port A GPIO 5, 5 V tolerant with analog switch, with alternate functions TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR and additional function ADC1_IN10.
15	PA6	bidirectional	Port A GPIO 6, 5 V tolerant with analog switch, with alternate functions TIM1_BKIN, SPI1_MISO, TIM16_CH1 and additional function ADC1_IN11.
16	PA7	bidirectional	Port A GPIO 7, 5 V tolerant Fm+ capable with analog switch, with alternate functions TIM1_CH1N, SPI1_MOSI, TIM17_CH1 and additional function ADC1_IN12.
17	PA8	bidirectional	Port A GPIO 8, 5 V tolerant with analog switch, with alternate functions MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT and additional function ADC1_IN15.
18	PA9	bidirectional	Port A GPIO 9, 5 V tolerant Fm+ capable, with alternate functions TIM1_CH2, I2C1_SCL, USART1_TX and additional function ADC1_IN16.
19	PB2	bidirectional	Port B GPIO 2, 5 V tolerant with analog switch, with alternate functions RTC_OUT, LPTIM1_OUT, SPI1_NSS.
20	VDD	power_in	Main digital power supply and I/O voltage, 2.0 to 3.6 V.
21	RF1	bidirectional	RF input/output for 2.4 GHz antenna connection through low-pass matching network.
22	VSSRF	power_in	RF ground/return path for RF subsystem, must be connected to GND plane for correct RF operation.
23	VDDRF	power_in	Dedicated RF power supply, must be connected to VDD, 2.0 to 3.6 V, requires 100 nF + 100 pF decoupling.
24	OSC_OUT	output	32 MHz main oscillator output, HSE source for radio and CPU clock.
25	OSC_IN	input	32 MHz main oscillator input from external crystal.
26	AT0	output	Reserved for production testing, must be kept unconnected.
27	AT1	output	Reserved for production testing, must be kept unconnected.
28	PB0	bidirectional	Port B GPIO 0, 3.6 V tolerant, with alternate function EXT_PA_TX; high frequency operation above 100 kHz may impact RF performance.
29	PB1	bidirectional	Port B GPIO 1, 3.6 V tolerant, with alternate function LPTIM2_IN1; high frequency operation above 100 kHz may impact RF performance.
30	PE4	bidirectional	Port E GPIO 4, 5 V tolerant.
31	VDD	power_in	Main digital power supply and I/O voltage, 2.0 to 3.6 V.
32	VSS	power_in	Ground return path for digital circuitry.
33	VDD	power_in	Main digital power supply and I/O voltage, 2.0 to 3.6 V.
34	VDD	power_in	Main digital power supply and I/O voltage, 2.0 to 3.6 V.
35	VDD	power_in	Main digital power supply and I/O voltage, 2.0 to 3.6 V.
36	PA10	bidirectional	Port A GPIO 10, 5 V tolerant Fm+ capable, with alternate functions TIM1_CH3, I2C1_SDA, USART1_RX, TIM17_BKIN.
37	PA11	bidirectional	Port A GPIO 11, 5 V tolerant, with alternate functions TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS.
38	PA12	bidirectional	Port A GPIO 12, 5 V tolerant, with alternate functions TIM1_ETR, SPI1_MOSI, USART1_RTS.
39	PA13	bidirectional	Port A GPIO 13 or JTMS-SWDIO serial wire debug I/O pin, 5 V tolerant, with alternate function IR_OUT.
40	VDD	power_in	Main digital power supply and I/O voltage, 2.0 to 3.6 V.
41	PA14	bidirectional	Port A GPIO 14 or JTCK-SWCLK serial wire debug clock pin, 5 V tolerant, with alternate functions LPTIM1_OUT, I2C1_SMBA.
42	PA15	bidirectional	Port A GPIO 15 or JTDI JTAG data input pin, 5 V tolerant, with alternate functions TIM2_CH1, TIM2_ETR, SPI1_NSS.
43	PB3	bidirectional	Port B GPIO 3 or JTDO-TRACESWO JTAG data output/SWO trace pin, 5 V tolerant with analog switch, with alternate functions TIM2_CH2, SPI1_SCK, USART1_RTS.
44	PB4	bidirectional	Port B GPIO 4 or NJTRST JTAG test reset pin, 5 V tolerant with analog switch, with alternate functions SPI1_MISO, USART1_CTS, TIM17_BKIN.
45	PB5	bidirectional	Port B GPIO 5, 5 V tolerant, with alternate functions LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, TIM16_BKIN.
46	PB6	bidirectional	Port B GPIO 6, 5 V tolerant Fm+ capable, with alternate functions LPTIM1_ETR, I2C1_SCL, USART1_TX, TIM16_CH1N, MCO.
47	PB7	bidirectional	Port B GPIO 7, 5 V tolerant Fm+ capable, with alternate functions LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, TIM17_CH1N and additional function PVD_IN.
48	VDD	power_in	Main digital power supply and I/O voltage, 2.0 to 3.6 V.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	UFQFPN-48(7x7)
Category	RF And Wireless
Pins	49

CAD (KiCad official)

Symbol: STM32WB50CGU5
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
3D model files: stm32wb50cgu5-etched.step / stm32wb50cgu5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32wb50cgu5.step / stm32wb50cgu5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (119 pp, sha256 8ab7d767054b0437, retrieved 2026-10-03, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF