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STM32WB15CCU6

Public Made by Adom

by adom

STMicroelectronics RF Transceiver ICs, UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32WB15CCU6

STMicroelectronics · RF Transceiver ICs · UFQFPN-48(7x7)

STM32WB15CCU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply voltage for RTC and backup registers (1.55 to 3.6 V)
2 PC14-OSC32_IN bidirectional GPIO Port C pin 14 or 32.768 kHz external oscillator input
3 PC15-OSC32_OUT bidirectional GPIO Port C pin 15 or 32.768 kHz external oscillator output
4 PH3-BOOT0 bidirectional GPIO Port H pin 3 / boot loader configuration (internal pull-down)
5 PB8 bidirectional GPIO Port B pin 8, Fm+ capable
6 PB9 bidirectional GPIO Port B pin 9, Fm+ capable
7 NRST bidirectional Active-low external reset pin with internal weak pull-up (also functions as PB11 GPIO)
8 VDDA power_in Analog supply voltage for ADC and comparator (1.62 to 3.6 V)
9 PA0 bidirectional GPIO Port A pin 0, analog switch function supplied by VDDA
10 PA1 bidirectional GPIO Port A pin 1, analog switch function supplied by VDDA
11 PA2 bidirectional GPIO Port A pin 2, analog switch function supplied by VDDA
12 PA3 bidirectional GPIO Port A pin 3, analog switch function supplied by VDDA
13 PA4 bidirectional GPIO Port A pin 4, analog switch function supplied by VDDA
14 PA5 bidirectional GPIO Port A pin 5, analog switch function supplied by VDDA
15 PA6 bidirectional GPIO Port A pin 6, analog switch function supplied by VDDA
16 PA7 bidirectional GPIO Port A pin 7, analog switch function supplied by VDDA
17 PA8 bidirectional GPIO Port A pin 8, analog switch function supplied by VDDA
18 PA9 bidirectional GPIO Port A pin 9, Fm+ capable, analog switch function supplied by VDDA
19 PB2 bidirectional GPIO Port B pin 2, analog switch function supplied by VDDA
20 VDD power_in Main supply voltage for digital core and I/Os (1.71 to 3.6 V)
21 RF1 bidirectional RF antenna input/output connected via low-pass impedance matching network to 2.4 GHz antenna
22 VSSRF power_in RF ground (must be connected to ground plane for correct RF operation)
23 VDDRF power_in RF dedicated supply voltage (must be connected to VDD)
24 OSC_OUT output 32 MHz main oscillator output for HSE system clock source
25 OSC_IN input 32 MHz oscillator input
26 AT0 unconnected Reserved for production, must be kept unconnected
27 AT1 unconnected Reserved for production, must be kept unconnected
28 PB0 bidirectional GPIO Port B pin 0, 3.6 V tolerant I/O, RF_TX_MOD_EXT_PA alternate function
29 PB1 bidirectional GPIO Port B pin 1, 3.6 V tolerant I/O (high frequency above 32 kHz may impact RF performance)
30 PE4 bidirectional GPIO Port E pin 4
31 VFBSMPS power_in SMPS step-down converter feedback voltage pin (1.4 to 3.6 V)
32 VSSSMPS power_in SMPS step-down converter ground
33 VLXSMPS power_in SMPS inductance switching node connected to external inductor
34 VDDSMPS power_in SMPS step-down converter supply input
35 VDD power_in Main supply voltage for digital core and I/Os (1.71 to 3.6 V)
36 PA10 bidirectional GPIO Port A pin 10, Fm+ capable
37 PA11 bidirectional GPIO Port A pin 11
38 PA12 bidirectional GPIO Port A pin 12
39 PA13 bidirectional GPIO Port A pin 13, JTAG-SWDIO interface after reset with internal pull-up
40 VDD power_in Main supply voltage for digital core and I/Os (1.71 to 3.6 V)
41 PA14 bidirectional GPIO Port A pin 14, JTAG-SWCLK interface after reset with internal pull-down
42 PA15 bidirectional GPIO Port A pin 15, JTAG-TDI interface after reset with internal pull-up
43 PB3 bidirectional GPIO Port B pin 3, JTAG-TDO/TRACESWO interface after reset
44 PB4 bidirectional GPIO Port B pin 4, JTAG-NJTRST interface after reset with internal pull-up
45 PB5 bidirectional GPIO Port B pin 5, configured as input with pull-up active under reset when NRST active
46 PB6 bidirectional GPIO Port B pin 6, Fm+ capable
47 PB7 bidirectional GPIO Port B pin 7, Fm+ capable, PVD_IN additional function
48 VDD power_in Main supply voltage for digital core and I/Os (1.71 to 3.6 V)
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category RF And Wireless
Pins 49

CAD (KiCad official)

  • Symbol: STM32WB15CCU6
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32wb15ccu6-etched.step / stm32wb15ccu6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32wb15ccu6.step / stm32wb15ccu6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (130 pp, sha256 0dd1c08bb27823a8, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF