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STM32WB10CCU5

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STMicroelectronics RF Transceiver ICs, UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32WB10CCU5

STMicroelectronics · RF Transceiver ICs · UFQFPN-48(7x7)

STM32WB10CCU5 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply that powers the RTC, LSE and backup registers from an external battery or supercapacitor, or from VDD when neither is present.
2 PC14-OSC32_IN bidirectional FT (5 V tolerant) I/O supplied through the power switch, which sinks only 3 mA, so output use is limited to 2 MHz with 30 pF maximum load and it must not drive current sources; alternate functions CM4_EVENTOUT, additional function OSC32_IN.
3 PC15-OSC32_OUT bidirectional FT (5 V tolerant) I/O supplied through the power switch, with the same output limits as PC14 (2 MHz maximum at 30 pF, no current-source use); alternate function CM4_EVENTOUT, additional function OSC32_OUT.
4 PH3-BOOT0 bidirectional FT (5 V tolerant) I/O also used as BOOT0; alternate functions LSCO and CM4_EVENTOUT.
5 PB8 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternate functions TIM1_CH2N, I2C1_SCL, TSC_G7_IO3 and CM4_EVENTOUT.
6 PB9 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternate functions TIM1_CH3N, I2C1_SDA, TSC_G7_IO4 and CM4_EVENTOUT.
7 NRST bidirectional Bidirectional reset pin with weak pull-up resistor; it is FT-tolerant when configured as the PB11 GPIO.
8 VDDA power_in External analog supply for the ADC, specified at 2.0 to 3.6 V; must be connected to VDD when the ADC is not used.
9 PA0 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions TIM2_CH1, TIM2_ETR and CM4_EVENTOUT, additional functions ADC1_IN5 and RTC_TAMP2/WKUP1; wake-up from Standby/Shutdown capable.
10 PA1 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions TIM2_CH2, I2C1_SMBA, SPI1_SCK and CM4_EVENTOUT, additional function ADC1_IN6.
11 PA2 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions LSCO, TIM2_CH3 and CM4_EVENTOUT, additional functions ADC1_IN7 and WKUP4; wake-up from Standby/Shutdown capable and carries LSCO in those modes.
12 PA3 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions TIM2_CH4 and CM4_EVENTOUT, additional function ADC1_IN8.
13 PA4 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions SPI1_NSS (boot), LPTIM2_OUT and CM4_EVENTOUT, additional function ADC1_IN9.
14 PA5 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions TIM2_CH1, TIM2_ETR, SPI1_MOSI, SPI1_SCK (boot), LPTIM2_ETR and CM4_EVENTOUT, additional function ADC1_IN10.
15 PA6 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions TIM1_BKIN, SPI1_MISO (boot) and CM4_EVENTOUT, additional function ADC1_IN11.
16 PA7 bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) with alternate functions TIM1_CH1N, SPI1_MOSI (boot) and CM4_EVENTOUT, additional function ADC1_IN2.
17 PA8 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT and CM4_EVENTOUT, additional function ADC1_IN3.
18 PA9 bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) with alternate functions TIM1_CH2, I2C1_SCL, USART1_TX (boot) and CM4_EVENTOUT, additional function ADC1_IN4.
19 PB2 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with alternate functions RTC_OUT, LPTIM1_OUT, SPI1_NSS and CM4_EVENTOUT, no additional function listed.
20 VDD power_in Main supply, 2.0 to 3.6 V, for I/Os, the internal regulator and system functions including RF, reset and clocks; VDDRF must always be connected to VDD.
21 RF1 bidirectional RF input/output that must be connected to the antenna through a low-pass matching network; use the nominal PCB layout.
22 VSSRF power_in RF ground that must be connected to GND, and to the ground plane through the exposed pad for correct RF operation.
23 VDDRF power_in Dedicated RF supply that must be connected to VDD.
24 OSC_OUT output 32 MHz main oscillator output, also used as the HSE source; use the nominal PCB layout per the reference design.
25 OSC_IN input 32 MHz main oscillator input, also used as the HSE source; use the nominal PCB layout per the reference design.
26 AT0 unconnected Reserved for production and must be kept unconnected.
27 AT1 unconnected Reserved for production and must be kept unconnected.
28 PB0 bidirectional TT (3.6 V tolerant) I/O with alternate functions RF_TX_MOD_EXT_PA and CM4_EVENTOUT; output speed must be set to 00 during RF operation because high frequency may impact RF performance.
29 PB1 bidirectional TT (3.6 V tolerant) I/O with alternate functions LPTIM2_IN1 and CM4_EVENTOUT; output speed must be set to 00 during RF operation because high frequency may impact RF performance.
30 PE4 bidirectional FT (5 V tolerant) I/O with alternate function CM4_EVENTOUT.
31 VDD power_in Main supply pin, 2.0 to 3.6 V, that must be wired together with the other VDD pins and VDDRF.
32 VSS power_in Ground pin.
33 VDD power_in Main supply pin, 2.0 to 3.6 V, that must be wired together with the other VDD pins and VDDRF.
34 VDD power_in Main supply pin, 2.0 to 3.6 V, that must be wired together with the other VDD pins and VDDRF.
35 VDD power_in Main supply pin, 2.0 to 3.6 V, that must be wired together with the other VDD pins and VDDRF.
36 PA10 bidirectional FT_f I/O (5 V tolerant, Fm+ capable) with alternate functions TIM1_CH3, I2C1_SDA, USART1_RX (boot), TSC_G7_IO2 and CM4_EVENTOUT.
37 PA11 bidirectional FT I/O (5 V tolerant) with alternate functions TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS and CM4_EVENTOUT.
38 PA12 bidirectional FT I/O (5 V tolerant) with alternate functions TIM1_ETR, SPI1_MOSI, USART1_RTS and CM4_EVENTOUT.
39 PA13 bidirectional FT I/O (5 V tolerant) defaulting after reset to JTMS-SWDIO with internal pull-up active; other alternate functions SPI1_MOSI, TSC_G7_IO1 and CM4_EVENTOUT.
40 VDD power_in Main supply pin, 2.0 to 3.6 V, that must be wired together with the other VDD pins and VDDRF.
41 PA14 bidirectional FT I/O (5 V tolerant) defaulting after reset to JTCK-SWCLK with internal pull-down active; other alternate functions LPTIM1_OUT, I2C1_SMBA, SPI1_NSS and CM4_EVENTOUT.
42 PA15 bidirectional FT I/O (5 V tolerant) defaulting after reset to JTDI with internal pull-up active; other alternate functions TIM2_CH1, TIM2_ETR, SPI1_NSS, MCO, TSC_G3_IO1 and CM4_EVENTOUT.
43 PB3 bidirectional FT I/O (5 V tolerant) with alternate functions JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, USART1_RTS and CM4_EVENTOUT.
44 PB4 bidirectional FT_f I/O (5 V tolerant, Fm+ capable) with alternate functions NJTRST, SPI1_MISO, USART1_CTS, TSC_G2_IO1 and CM4_EVENTOUT; internal pull-up active after reset.
45 PB5 bidirectional FT I/O (5 V tolerant) with alternate functions LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, TSC_G2_IO2 and CM4_EVENTOUT; configured as input with pull-up active under reset.
46 PB6 bidirectional FT_f I/O (5 V tolerant, Fm+ capable) with alternate functions MCO, LPTIM1_ETR, I2C1_SCL (boot), SPI1_NSS, USART1_TX, TSC_G2_IO3 and CM4_EVENTOUT.
47 PB7 bidirectional FT_f I/O (5 V tolerant, Fm+ capable) with alternate functions LPTIM1_IN2, TIM1_BKIN, I2C1_SDA (boot), USART1_RX, TSC_G2_IO4, TIM1_CH3 and CM4_EVENTOUT, additional function PVD_IN.
48 VDD power_in Main supply pin, 2.0 to 3.6 V, that must be wired together with the other VDD pins and VDDRF.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category RF And Wireless
Pins 49

CAD (KiCad official)

  • Symbol: STM32WB10CCU5
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32wb10ccu5-etched.step / stm32wb10ccu5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32wb10ccu5.step / stm32wb10ccu5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (111 pp, sha256 6f2a5658c6c14f5e, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF