component
STM32U575RIT6Q
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
main
STM32U575RIT6Q
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32U575RIT6Q from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup domain supply for RTC, backup registers and backup SRAM (VBAT mode). |
| 2 | PC13 | bidirectional | FT I/O supplied by VSW with EVENTOUT; as output limited to 2 MHz, 30 pF, 3 mA shared with PC14/PC15; additional functions WKUP2, RTC_TS/RTC_OUT1, TAMP_IN1/TAMP_OUT2. |
| 3 | PC14-OSC32_IN | bidirectional | FT_o I/O supplied by VSW, EVENTOUT, additional function OSC32_IN (LSE crystal input); output limited to 2 MHz, 30 pF. |
| 4 | PC15-OSC32_OUT | bidirectional | FT_o I/O supplied by VSW, EVENTOUT, additional function OSC32_OUT (LSE crystal output); output limited to 2 MHz, 30 pF. |
| 5 | PH0-OSC_IN | bidirectional | FT I/O with EVENTOUT and additional function OSC_IN (HSE oscillator input). |
| 6 | PH1-OSC_OUT | bidirectional | FT I/O with EVENTOUT and additional function OSC_OUT (HSE oscillator output). |
| 7 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 8 | PC0 | bidirectional | FT_fha I/O with LPTIM1_IN1, I2C3_SCL, SPI2_RDY, MDF1_SDI4, LPUART1_RX, SDMMC1_D5, SAI2_FS_A, EVENTOUT; analog ADC1_IN1, ADC4_IN1. |
| 9 | PC1 | bidirectional | FT_fhav I/O with TRACED0, LPTIM1_CH1, SPI2_MOSI, I2C3_SDA, MDF1_CKI4, LPUART1_TX, SDMMC2_CK, SAI1_SD_A; analog ADC1_IN2, ADC4_IN2. |
| 10 | PC2 | bidirectional | FT_ha I/O with LPTIM1_IN2, SPI2_MISO, MDF1_CCK1, LPGPIO1_P5, EVENTOUT; analog ADC1_IN3, ADC4_IN3. |
| 11 | PC3 | bidirectional | FT_ha I/O with LPTIM1_ETR, LPTIM3_CH1, SAI1_D1, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR; analog ADC1_IN4, ADC4_IN4. |
| 12 | VSSA | power_in | Analog ground. |
| 13 | VDDA | power_in | Analog supply for ADCs, DACs, OPAMPs, COMPs and VREFBUF. |
| 14 | PA0 | bidirectional | FT_hat I/O with TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SDMMC2_CMD; additional OPAMP1_VINP, ADC1_IN5, WKUP1, TAMP_IN2/TAMP_OUT1. |
| 15 | PA1 | bidirectional | FT_hat I/O with LPTIM1_CH2, TIM2_CH2, TIM5_CH2, SPI1_SCK, USART2_RTS_DE, UART4_RX; additional OPAMP1_VINM, ADC1_IN6, WKUP3, TAMP_IN5/TAMP_OUT4. |
| 16 | PA2 | bidirectional | FT_ha I/O with TIM2_CH3, TIM5_CH3, USART2_TX(boot), LPUART1_TX, UCPD1_FRSTX1; additional COMP1_INP3, ADC1_IN7, WKUP4/LSCO. |
| 17 | PA3 | bidirectional | TT_hav I/O with TIM2_CH4, TIM5_CH4, SAI1_CK1, USART2_RX(boot), LPUART1_RX; additional OPAMP1_VOUT, ADC1_IN8, WKUP5. |
| 18 | VSS | power_in | Digital ground. |
| 19 | VDD | power_in | Digital supply voltage. |
| 20 | PA4 | bidirectional | TT_ha I/O with SPI1_NSS(boot), SPI3_NSS, USART2_CK, DCMI_HSYNC/PSSI_DE, LPTIM2_CH1; additional ADC1_IN9, ADC4_IN9, DAC1_OUT1, WKUP2. |
| 21 | PA5 | bidirectional | TT_a I/O with CSLEEP, TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK(boot), USART3_RX; additional ADC1_IN10, ADC4_IN10, DAC1_OUT2, WKUP6. |
| 22 | PA6 | bidirectional | FT_ha I/O with CDSTOP, TIM1_BKIN, TIM3_CH1, SPI1_MISO(boot), USART3_CTS, LPUART1_CTS; additional OPAMP2_VINP, ADC1_IN11, ADC4_IN11, WKUP7. |
| 23 | PA7 | bidirectional | FT_fha I/O with SRDSTOP, TIM1_CH1N, TIM3_CH2, I2C3_SCL, SPI1_MOSI(boot), USART3_TX; additional OPAMP2_VINM, ADC1_IN12, ADC4_IN20, WKUP8. |
| 24 | PB0 | bidirectional | TT_ha I/O with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LPTIM3_CH1, SPI1_NSS, USART3_CK, COMP1_OUT; additional OPAMP2_VOUT, ADC1_IN15, ADC4_IN18. |
| 25 | PB1 | bidirectional | FT_ha I/O with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LPTIM3_CH2, MDF1_SDI0, USART3_RTS_DE; additional COMP1_INM1, ADC1_IN16, ADC4_IN19, WKUP4. |
| 26 | PB2 | bidirectional | FT_hat I/O with LPTIM1_CH1, TIM8_CH4N, I2C3_SMBA, SPI1_RDY, MDF1_CKI0, UCPD1_FRSTX1; additional COMP1_INP2, ADC1_IN17, WKUP1, RTC_OUT2. |
| 27 | PB10 | bidirectional | FT_fhv I/O with TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL(boot), SPI2_SCK, USART3_TX, LPUART1_RX, COMP1_OUT; additional WKUP8. |
| 28 | VLXSMPS | power_out | SMPS step-down converter switching node, connected to VDD11 through a 2.2 µH inductor (ISAT > 0.5 A, DCR < 200 mΩ). |
| 29 | VDDSMPS | power_in | SMPS step-down converter input supply, decoupled with 10 µF ±20% (ESR < 10 mΩ at 3 MHz, rated ≥ 10 V). |
| 30 | VSSSMPS | power_in | SMPS step-down converter ground. |
| 31 | VDD11 | power_in | 1.1 V core supply from SMPS output, with 2 × 2.2 µF ±20% capacitors (ESR < 20 mΩ at 3 MHz, rated ≥ 10 V). |
| 32 | VSS | power_in | Digital ground. |
| 33 | VDD | power_in | Digital supply voltage. |
| 34 | PB13 | bidirectional | FT_fa I/O with TIM1_CH1N, LPTIM3_IN1, I2C2_SCL, SPI2_SCK(boot), MDF1_CKI1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SAI2_SCK_A. |
| 35 | PB14 | bidirectional | FT_fda I/O with TIM1_CH2N, LPTIM3_ETR, TIM8_CH2N, I2C2_SDA, SPI2_MISO(boot), MDF1_SDI2, USART3_RTS_DE, SDMMC2_D0; additional UCPD1_DBCC2. |
| 36 | PB15 | bidirectional | FT_c I/O with RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI(boot), MDF1_CKI2, SDMMC2_D1, SAI2_SD_A; additional UCPD1_CC2, WKUP7; 5.1 kΩ dead-battery pull-down possible after reset. |
| 37 | PC6 | bidirectional | FT_a I/O with CSLEEP, TIM3_CH1, TIM8_CH1, MDF1_CKI3, SDMMC1_D0DIR, TSC_G4_IO1, DCMI_D0/PSSI_D0, SDMMC2_D6, SDMMC1_D6, SAI2_MCLK_A. |
| 38 | PC7 | bidirectional | FT_a I/O with CDSTOP, TIM3_CH2, TIM8_CH2, MDF1_SDI3, SDMMC1_D123DIR, TSC_G4_IO2, DCMI_D1/PSSI_D1, SDMMC2_D7, SDMMC1_D7, SAI2_MCLK_B. |
| 39 | PC8 | bidirectional | FT_a I/O with SRDSTOP, TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2/PSSI_D2, SDMMC1_D0, LPTIM3_CH1. |
| 40 | PC9 | bidirectional | FT_a I/O with TRACED0, TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3/PSSI_D3, TSC_G4_IO4, OTG_FS_NOE, SDMMC1_D1, LPTIM3_CH2. |
| 41 | PA8 | bidirectional | FT_hv I/O with MCO, TIM1_CH1, SAI1_CK2, SPI1_RDY, USART1_CK, OTG_FS_SOF, TRACECLK, SAI1_SCK_A, LPTIM2_CH1. |
| 42 | PA9 | bidirectional | FT_u I/O with TIM1_CH2, SPI2_SCK, DCMI_D0/PSSI_D0, USART1_TX(boot), SAI1_FS_A, TIM15_BKIN; additional OTG_FS_VBUS. |
| 43 | PA10 | bidirectional | FT_u I/O with CRS_SYNC, TIM1_CH3, LPTIM2_IN2, SAI1_D1, DCMI_D1/PSSI_D1, USART1_RX(boot), OTG_FS_ID, SAI1_SD_A, TIM17_BKIN. |
| 44 | PA11 | bidirectional | FT_u I/O with TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, FDCAN1_RX, OTG_FS_DM(boot). |
| 45 | PA12 | bidirectional | FT_u I/O with TIM1_ETR, SPI1_MOSI, OCTOSPIM_P2_NCS, USART1_RTS_DE, FDCAN1_TX, OTG_FS_DP(boot). |
| 46 | PA13 (JTMS/SWDIO) | bidirectional | FT I/O configured as JTMS/SWDIO after reset with internal pull-up; alternates IR_OUT, OTG_FS_NOE, SAI1_SD_B. |
| 47 | VSS | power_in | Digital ground. |
| 48 | VDDUSB | power_in | Independent USB transceiver supply. |
| 49 | PA14 (JTCK/SWCLK) | bidirectional | FT I/O configured as JTCK/SWCLK after reset with internal pull-down; alternates LPTIM1_CH1, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SAI1_FS_B. |
| 50 | PA15 (JTDI) | bidirectional | FT_c I/O configured as JTDI after reset with internal pull-up; alternates TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, SAI2_FS_B; additional UCPD1_CC1. |
| 51 | PC10 | bidirectional | FT_a I/O with TRACED1, LPTIM3_ETR, ADF1_CCK1, SPI3_SCK, USART3_TX(boot), UART4_TX, TSC_G3_IO2, DCMI_D8/PSSI_D8, SDMMC1_D2, SAI2_SCK_B. |
| 52 | PC11 | bidirectional | FT_ha I/O with LPTIM3_IN1, ADF1_SDI0, OCTOSPIM_P1_NCS, SPI3_MISO, USART3_RX(boot), UART4_RX, TSC_G3_IO3, SDMMC1_D3, SAI2_MCLK_B. |
| 53 | PC12 | bidirectional | FT_hav I/O with TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9/PSSI_D9, SDMMC1_CK, SAI2_SD_B. |
| 54 | PD2 | bidirectional | FT I/O with TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11/PSSI_D11, SDMMC1_CMD, LPTIM4_ETR. |
| 55 | PB3 (JTDO/TRACESWO) | bidirectional | FT_fa I/O configured as JTDO/TRACESWO after reset; alternates TIM2_CH2, LPTIM1_CH1, ADF1_CCK0, I2C1_SDA, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SDMMC2_D2; additional COMP2_INM2. |
| 56 | PB4 (NJTRST) | bidirectional | FT_fa I/O configured as NJTRST after reset with internal pull-up; alternates LPTIM1_CH2, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE; additional COMP2_INP1. |
| 57 | PB5 | bidirectional | FT_havd I/O with LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI(boot), USART1_CK, UART5_CTS, COMP2_OUT; additional UCPD1_DBCC1, WKUP6. |
| 58 | PB6 | bidirectional | FT_fa I/O with LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL(boot), I2C4_SCL, MDF1_SDI5, USART1_TX; additional COMP2_INP2, WKUP3. |
| 59 | PB7 | bidirectional | FT_fhav I/O with LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA(boot), I2C4_SDA, MDF1_CKI5, USART1_RX, UART4_CTS; additional COMP2_INM1, PVD_IN, WKUP4. |
| 60 | PH3-BOOT0 | bidirectional | FT I/O with EVENTOUT, used as BOOT0 boot mode selection input. |
| 61 | PB8 | bidirectional | FT_f I/O with TIM4_CH3, SAI1_CK1, I2C1_SCL, MDF1_CCK0, SPI3_RDY, SDMMC1_CKIN, FDCAN1_RX(boot), SAI1_MCLK_A, TIM16_CH1; additional WKUP5. |
| 62 | VDD11 | power_in | 1.1 V core supply from SMPS output, with 2 × 2.2 µF ±20% capacitors (ESR < 20 mΩ at 3 MHz, rated ≥ 10 V). |
| 63 | VSS | power_in | Digital ground. |
| 64 | VDD | power_in | Digital supply voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32U575RIT6Q - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32u575rit6q-etched.step/stm32u575rit6q-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32u575rit6q.step/stm32u575rit6q.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (338 pp, sha256
6e54872aba50deff, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM32U575RIT6Q
**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32U575RIT6Q from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup domain supply for RTC, backup registers and backup SRAM (VBAT mode). |
| 2 | PC13 | bidirectional | FT I/O supplied by VSW with EVENTOUT; as output limited to 2 MHz, 30 pF, 3 mA shared with PC14/PC15; additional functions WKUP2, RTC_TS/RTC_OUT1, TAMP_IN1/TAMP_OUT2. |
| 3 | PC14-OSC32_IN | bidirectional | FT_o I/O supplied by VSW, EVENTOUT, additional function OSC32_IN (LSE crystal input); output limited to 2 MHz, 30 pF. |
| 4 | PC15-OSC32_OUT | bidirectional | FT_o I/O supplied by VSW, EVENTOUT, additional function OSC32_OUT (LSE crystal output); output limited to 2 MHz, 30 pF. |
| 5 | PH0-OSC_IN | bidirectional | FT I/O with EVENTOUT and additional function OSC_IN (HSE oscillator input). |
| 6 | PH1-OSC_OUT | bidirectional | FT I/O with EVENTOUT and additional function OSC_OUT (HSE oscillator output). |
| 7 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 8 | PC0 | bidirectional | FT_fha I/O with LPTIM1_IN1, I2C3_SCL, SPI2_RDY, MDF1_SDI4, LPUART1_RX, SDMMC1_D5, SAI2_FS_A, EVENTOUT; analog ADC1_IN1, ADC4_IN1. |
| 9 | PC1 | bidirectional | FT_fhav I/O with TRACED0, LPTIM1_CH1, SPI2_MOSI, I2C3_SDA, MDF1_CKI4, LPUART1_TX, SDMMC2_CK, SAI1_SD_A; analog ADC1_IN2, ADC4_IN2. |
| 10 | PC2 | bidirectional | FT_ha I/O with LPTIM1_IN2, SPI2_MISO, MDF1_CCK1, LPGPIO1_P5, EVENTOUT; analog ADC1_IN3, ADC4_IN3. |
| 11 | PC3 | bidirectional | FT_ha I/O with LPTIM1_ETR, LPTIM3_CH1, SAI1_D1, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR; analog ADC1_IN4, ADC4_IN4. |
| 12 | VSSA | power_in | Analog ground. |
| 13 | VDDA | power_in | Analog supply for ADCs, DACs, OPAMPs, COMPs and VREFBUF. |
| 14 | PA0 | bidirectional | FT_hat I/O with TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SDMMC2_CMD; additional OPAMP1_VINP, ADC1_IN5, WKUP1, TAMP_IN2/TAMP_OUT1. |
| 15 | PA1 | bidirectional | FT_hat I/O with LPTIM1_CH2, TIM2_CH2, TIM5_CH2, SPI1_SCK, USART2_RTS_DE, UART4_RX; additional OPAMP1_VINM, ADC1_IN6, WKUP3, TAMP_IN5/TAMP_OUT4. |
| 16 | PA2 | bidirectional | FT_ha I/O with TIM2_CH3, TIM5_CH3, USART2_TX(boot), LPUART1_TX, UCPD1_FRSTX1; additional COMP1_INP3, ADC1_IN7, WKUP4/LSCO. |
| 17 | PA3 | bidirectional | TT_hav I/O with TIM2_CH4, TIM5_CH4, SAI1_CK1, USART2_RX(boot), LPUART1_RX; additional OPAMP1_VOUT, ADC1_IN8, WKUP5. |
| 18 | VSS | power_in | Digital ground. |
| 19 | VDD | power_in | Digital supply voltage. |
| 20 | PA4 | bidirectional | TT_ha I/O with SPI1_NSS(boot), SPI3_NSS, USART2_CK, DCMI_HSYNC/PSSI_DE, LPTIM2_CH1; additional ADC1_IN9, ADC4_IN9, DAC1_OUT1, WKUP2. |
| 21 | PA5 | bidirectional | TT_a I/O with CSLEEP, TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK(boot), USART3_RX; additional ADC1_IN10, ADC4_IN10, DAC1_OUT2, WKUP6. |
| 22 | PA6 | bidirectional | FT_ha I/O with CDSTOP, TIM1_BKIN, TIM3_CH1, SPI1_MISO(boot), USART3_CTS, LPUART1_CTS; additional OPAMP2_VINP, ADC1_IN11, ADC4_IN11, WKUP7. |
| 23 | PA7 | bidirectional | FT_fha I/O with SRDSTOP, TIM1_CH1N, TIM3_CH2, I2C3_SCL, SPI1_MOSI(boot), USART3_TX; additional OPAMP2_VINM, ADC1_IN12, ADC4_IN20, WKUP8. |
| 24 | PB0 | bidirectional | TT_ha I/O with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LPTIM3_CH1, SPI1_NSS, USART3_CK, COMP1_OUT; additional OPAMP2_VOUT, ADC1_IN15, ADC4_IN18. |
| 25 | PB1 | bidirectional | FT_ha I/O with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LPTIM3_CH2, MDF1_SDI0, USART3_RTS_DE; additional COMP1_INM1, ADC1_IN16, ADC4_IN19, WKUP4. |
| 26 | PB2 | bidirectional | FT_hat I/O with LPTIM1_CH1, TIM8_CH4N, I2C3_SMBA, SPI1_RDY, MDF1_CKI0, UCPD1_FRSTX1; additional COMP1_INP2, ADC1_IN17, WKUP1, RTC_OUT2. |
| 27 | PB10 | bidirectional | FT_fhv I/O with TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL(boot), SPI2_SCK, USART3_TX, LPUART1_RX, COMP1_OUT; additional WKUP8. |
| 28 | VLXSMPS | power_out | SMPS step-down converter switching node, connected to VDD11 through a 2.2 µH inductor (ISAT > 0.5 A, DCR < 200 mΩ). |
| 29 | VDDSMPS | power_in | SMPS step-down converter input supply, decoupled with 10 µF ±20% (ESR < 10 mΩ at 3 MHz, rated ≥ 10 V). |
| 30 | VSSSMPS | power_in | SMPS step-down converter ground. |
| 31 | VDD11 | power_in | 1.1 V core supply from SMPS output, with 2 × 2.2 µF ±20% capacitors (ESR < 20 mΩ at 3 MHz, rated ≥ 10 V). |
| 32 | VSS | power_in | Digital ground. |
| 33 | VDD | power_in | Digital supply voltage. |
| 34 | PB13 | bidirectional | FT_fa I/O with TIM1_CH1N, LPTIM3_IN1, I2C2_SCL, SPI2_SCK(boot), MDF1_CKI1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SAI2_SCK_A. |
| 35 | PB14 | bidirectional | FT_fda I/O with TIM1_CH2N, LPTIM3_ETR, TIM8_CH2N, I2C2_SDA, SPI2_MISO(boot), MDF1_SDI2, USART3_RTS_DE, SDMMC2_D0; additional UCPD1_DBCC2. |
| 36 | PB15 | bidirectional | FT_c I/O with RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI(boot), MDF1_CKI2, SDMMC2_D1, SAI2_SD_A; additional UCPD1_CC2, WKUP7; 5.1 kΩ dead-battery pull-down possible after reset. |
| 37 | PC6 | bidirectional | FT_a I/O with CSLEEP, TIM3_CH1, TIM8_CH1, MDF1_CKI3, SDMMC1_D0DIR, TSC_G4_IO1, DCMI_D0/PSSI_D0, SDMMC2_D6, SDMMC1_D6, SAI2_MCLK_A. |
| 38 | PC7 | bidirectional | FT_a I/O with CDSTOP, TIM3_CH2, TIM8_CH2, MDF1_SDI3, SDMMC1_D123DIR, TSC_G4_IO2, DCMI_D1/PSSI_D1, SDMMC2_D7, SDMMC1_D7, SAI2_MCLK_B. |
| 39 | PC8 | bidirectional | FT_a I/O with SRDSTOP, TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2/PSSI_D2, SDMMC1_D0, LPTIM3_CH1. |
| 40 | PC9 | bidirectional | FT_a I/O with TRACED0, TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3/PSSI_D3, TSC_G4_IO4, OTG_FS_NOE, SDMMC1_D1, LPTIM3_CH2. |
| 41 | PA8 | bidirectional | FT_hv I/O with MCO, TIM1_CH1, SAI1_CK2, SPI1_RDY, USART1_CK, OTG_FS_SOF, TRACECLK, SAI1_SCK_A, LPTIM2_CH1. |
| 42 | PA9 | bidirectional | FT_u I/O with TIM1_CH2, SPI2_SCK, DCMI_D0/PSSI_D0, USART1_TX(boot), SAI1_FS_A, TIM15_BKIN; additional OTG_FS_VBUS. |
| 43 | PA10 | bidirectional | FT_u I/O with CRS_SYNC, TIM1_CH3, LPTIM2_IN2, SAI1_D1, DCMI_D1/PSSI_D1, USART1_RX(boot), OTG_FS_ID, SAI1_SD_A, TIM17_BKIN. |
| 44 | PA11 | bidirectional | FT_u I/O with TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, FDCAN1_RX, OTG_FS_DM(boot). |
| 45 | PA12 | bidirectional | FT_u I/O with TIM1_ETR, SPI1_MOSI, OCTOSPIM_P2_NCS, USART1_RTS_DE, FDCAN1_TX, OTG_FS_DP(boot). |
| 46 | PA13 (JTMS/SWDIO) | bidirectional | FT I/O configured as JTMS/SWDIO after reset with internal pull-up; alternates IR_OUT, OTG_FS_NOE, SAI1_SD_B. |
| 47 | VSS | power_in | Digital ground. |
| 48 | VDDUSB | power_in | Independent USB transceiver supply. |
| 49 | PA14 (JTCK/SWCLK) | bidirectional | FT I/O configured as JTCK/SWCLK after reset with internal pull-down; alternates LPTIM1_CH1, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SAI1_FS_B. |
| 50 | PA15 (JTDI) | bidirectional | FT_c I/O configured as JTDI after reset with internal pull-up; alternates TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, SAI2_FS_B; additional UCPD1_CC1. |
| 51 | PC10 | bidirectional | FT_a I/O with TRACED1, LPTIM3_ETR, ADF1_CCK1, SPI3_SCK, USART3_TX(boot), UART4_TX, TSC_G3_IO2, DCMI_D8/PSSI_D8, SDMMC1_D2, SAI2_SCK_B. |
| 52 | PC11 | bidirectional | FT_ha I/O with LPTIM3_IN1, ADF1_SDI0, OCTOSPIM_P1_NCS, SPI3_MISO, USART3_RX(boot), UART4_RX, TSC_G3_IO3, SDMMC1_D3, SAI2_MCLK_B. |
| 53 | PC12 | bidirectional | FT_hav I/O with TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9/PSSI_D9, SDMMC1_CK, SAI2_SD_B. |
| 54 | PD2 | bidirectional | FT I/O with TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11/PSSI_D11, SDMMC1_CMD, LPTIM4_ETR. |
| 55 | PB3 (JTDO/TRACESWO) | bidirectional | FT_fa I/O configured as JTDO/TRACESWO after reset; alternates TIM2_CH2, LPTIM1_CH1, ADF1_CCK0, I2C1_SDA, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SDMMC2_D2; additional COMP2_INM2. |
| 56 | PB4 (NJTRST) | bidirectional | FT_fa I/O configured as NJTRST after reset with internal pull-up; alternates LPTIM1_CH2, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE; additional COMP2_INP1. |
| 57 | PB5 | bidirectional | FT_havd I/O with LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI(boot), USART1_CK, UART5_CTS, COMP2_OUT; additional UCPD1_DBCC1, WKUP6. |
| 58 | PB6 | bidirectional | FT_fa I/O with LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL(boot), I2C4_SCL, MDF1_SDI5, USART1_TX; additional COMP2_INP2, WKUP3. |
| 59 | PB7 | bidirectional | FT_fhav I/O with LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA(boot), I2C4_SDA, MDF1_CKI5, USART1_RX, UART4_CTS; additional COMP2_INM1, PVD_IN, WKUP4. |
| 60 | PH3-BOOT0 | bidirectional | FT I/O with EVENTOUT, used as BOOT0 boot mode selection input. |
| 61 | PB8 | bidirectional | FT_f I/O with TIM4_CH3, SAI1_CK1, I2C1_SCL, MDF1_CCK0, SPI3_RDY, SDMMC1_CKIN, FDCAN1_RX(boot), SAI1_MCLK_A, TIM16_CH1; additional WKUP5. |
| 62 | VDD11 | power_in | 1.1 V core supply from SMPS output, with 2 × 2.2 µF ±20% capacitors (ESR < 20 mΩ at 3 MHz, rated ≥ 10 V). |
| 63 | VSS | power_in | Digital ground. |
| 64 | VDD | power_in | Digital supply voltage. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## CAD (KiCad official)
- Symbol: `STM32U575RIT6Q`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm32u575rit6q-etched.step` / `stm32u575rit6q-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32u575rit6q.step` / `stm32u575rit6q.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603011000698892288) (338 pp, sha256 `6e54872aba50deff`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm32u575rit6q-datasheet.pdf)