component
STM32L4Q5CGT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32L4Q5CGT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM32L4Q5CGT6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC, 32 kHz oscillator and backup registers, specified from 1.55 V to 3.6 V and used when VDD is not present. |
| 2 | PC13 | bidirectional | GPIO supplied through the power switch that sinks only 3 mA, so output use is limited to 2 MHz with a 30 pF load and it must not be used as a current source; it also carries RTC_TAMP1/RTC_TS/RTC_OUT and WKUP2. |
| 3 | PC14-OSC32_IN | bidirectional | GPIO supplied through the power switch with the same 3 mA and 2 MHz / 30 pF output limits, and it is the 32 kHz LSE oscillator input OSC32_IN. |
| 4 | PC15-OSC32_OUT | bidirectional | GPIO supplied through the power switch with the same 3 mA and 2 MHz / 30 pF output limits, and it is the 32 kHz LSE oscillator output OSC32_OUT. |
| 5 | PH0-OSC_IN | bidirectional | 5 V-tolerant (FT) GPIO that doubles as the high-speed external oscillator input OSC_IN. |
| 6 | PH1-OSC_OUT | bidirectional | 5 V-tolerant (FT) GPIO that doubles as the high-speed external oscillator output OSC_OUT. |
| 7 | NRST | bidirectional | Bidirectional reset pin with an embedded weak pull-up resistor. |
| 8 | VSSA/VREF- | power_in | Analog ground pin; on this package VREF- is bonded to VSSA and must always be equal to VSSA. |
| 9 | VDDA/VREF+ | power_in | Analog supply (VDDA, 1.62 V to 3.6 V for ADC/COMP, 1.8 V for DAC/OPAMP); VREF+ is double-bonded to VDDA on this package, so the internal voltage reference buffer is not available and must be kept disabled. |
| 10 | PA0 | bidirectional | 5 V-tolerant GPIO with analog switch function supplied by VDDA; additional functions are OPAMP1_VINP, ADC12_IN5, RTC_TAMP2 and WKUP1. |
| 11 | PA1 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog switch function supplied by VDDA; additional functions are OPAMP1_VINM and ADC12_IN6. |
| 12 | PA2 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog switch function supplied by VDDA; additional functions are ADC12_IN7 and WKUP4/LSCO. |
| 13 | PA3 | bidirectional | 3.6 V-tolerant (TT) GPIO with analog switch function supplied by VDDA; additional functions are OPAMP1_VOUT and ADC12_IN8. |
| 14 | PA4 | bidirectional | 3.6 V-tolerant (TT) GPIO with analog switch function supplied by VDDA; additional functions are ADC12_IN9 and DAC1_OUT1, and its injected current is limited to -5/0 mA. |
| 15 | PA5 | bidirectional | 3.6 V-tolerant (TT) GPIO with analog switch function supplied by VDDA; additional functions are ADC12_IN10 and DAC1_OUT2, and its injected current is limited to -5/0 mA. |
| 16 | PA6 | bidirectional | 5 V-tolerant GPIO with analog switch function supplied by VDDA; additional functions are OPAMP2_VINP and ADC12_IN11, and it also carries TIM1_BKIN and TIM8_BKIN. |
| 17 | PA7 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog switch function supplied by VDDA; additional functions are OPAMP2_VINM and ADC12_IN12. |
| 18 | PB0 | bidirectional | 3.6 V-tolerant (TT) GPIO with analog switch function supplied by VDDA; additional functions are OPAMP2_VOUT and ADC12_IN15. |
| 19 | PB1 | bidirectional | 5 V-tolerant GPIO with analog switch function supplied by VDDA; additional functions are COMP1_INM and ADC12_IN16. |
| 20 | PB2 | bidirectional | 5 V-tolerant GPIO with analog switch function supplied by VDDA; additional function is COMP1_INP, and it also carries RTC_OUT2 and LPTIM1_OUT. |
| 21 | PB10 | bidirectional | 5 V-tolerant Fm+ capable GPIO; alternate functions include TIM2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX and LPUART1_RX. |
| 22 | PB11 | bidirectional | 5 V-tolerant Fm+ capable GPIO; alternate functions include TIM2_CH4, I2C2_SDA, USART3_RX, LPUART1_TX and COMP2_OUT. |
| 23 | VSS | power_in | Digital ground pin; all VSS pins must be connected to the board ground and their mutual difference kept within 50 mV. |
| 24 | VDD | power_in | Main digital supply pin, 1.71 V to 3.6 V, with variations between VDD pins kept within 50 mV. |
| 25 | PB12 | bidirectional | 5 V-tolerant GPIO; alternate functions include TIM1_BKIN, I2C2_SMBA, SPI2_NSS, USART3_CK and LPUART1_RTS_DE. |
| 26 | PB13 | bidirectional | 5 V-tolerant Fm+ capable GPIO; alternate functions include TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS_NSS and LPUART1_CTS. |
| 27 | PB14 | bidirectional | 5 V-tolerant Fm+ capable GPIO; alternate functions include TIM1_CH2N, I2C2_SDA, SPI2_MISO, USART3_RTS_DE and SDMMC2_D0. |
| 28 | PB15 | bidirectional | 5 V-tolerant GPIO; alternate functions include RTC_REFIN, TIM1_CH3N, SPI2_MOSI, SDMMC2_D1 and SAI2_SD_A. |
| 29 | PA8 | bidirectional | 5 V-tolerant Fm+ capable GPIO; alternate functions include MCO, TIM1_CH1, USART1_CK and OTG_FS_SOF. |
| 30 | PA9 | bidirectional | 5 V-tolerant Fm+ capable GPIO with USB function supplied by VDDUSB; alternate functions include TIM1_CH2, SPI2_SCK, USART1_TX and OTG_FS_VBUS. |
| 31 | PA10 | bidirectional | 5 V-tolerant Fm+ capable GPIO with USB function supplied by VDDUSB; alternate functions include TIM1_CH3, SAI1_D1, USART1_RX and OTG_FS_ID. |
| 32 | PA11 | bidirectional | 5 V-tolerant GPIO with USB function supplied by VDDUSB; alternate functions include TIM1_CH4, SPI1_MISO, USART1_CTS_NSS, CAN1_RX and OTG_FS_DM. |
| 33 | PA12 | bidirectional | 5 V-tolerant GPIO with USB function supplied by VDDUSB; alternate functions include TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX and OTG_FS_DP. |
| 34 | PA13 (JTMS/SWDIO) | bidirectional | 5 V-tolerant GPIO that after reset is the JTMS/SWDIO debug pin with its internal pull-up activated. |
| 35 | VSS | power_in | Digital ground pin; all VSS pins must be connected to the board ground and their mutual difference kept within 50 mV. |
| 36 | VDDUSB | power_in | USB transceiver supply, 3.0 V to 3.6 V when USB is used (may be 0 V to 3.6 V when USB is not used). |
| 37 | PA14 (JTCK/SWCLK) | bidirectional | 5 V-tolerant GPIO that after reset is the JTCK/SWCLK debug pin with its internal pull-down activated. |
| 38 | PA15 (JTDI) | bidirectional | 5 V-tolerant GPIO that after reset is the JTDI debug pin with its internal pull-up activated. |
| 39 | PB3 (JTDO/TRACESWO) | bidirectional | 5 V-tolerant GPIO with analog switch function supplied by VDDA; alternate function JTDO/TRACESWO with additional function COMP2_INM. |
| 40 | PB4 (NJTRST) | bidirectional | 5 V-tolerant Fm+ capable GPIO that after reset is the NJTRST debug pin with its internal pull-up activated; additional function COMP2_INP. |
| 41 | PB5 | bidirectional | 5 V-tolerant GPIO with analog switch function supplied by VDDA; alternate functions include LPTIM1_IN1, TIM3_CH2, SPI1_MOSI, SPI3_MOSI and COMP2_OUT. |
| 42 | PB6 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog switch function supplied by VDDA; additional function COMP2_INP, and alternate functions include I2C1_SCL and USART1_TX. |
| 43 | PB7 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog switch function supplied by VDDA; additional functions are COMP2_INM and PVD_IN, and alternate functions include I2C1_SDA and USART1_RX. |
| 44 | PH3-BOOT0 | bidirectional | 5 V-tolerant (FT) GPIO used as the BOOT0 input; the BOOT0 value comes from this pin or from an option bit depending on a user option bit. |
| 45 | PB8 | bidirectional | 5 V-tolerant Fm+ capable GPIO; alternate functions include TIM4_CH3, SAI1_CK1, I2C1_SCL, CAN1_RX and SDMMC1_D4. |
| 46 | PB9 | bidirectional | 5 V-tolerant Fm+ capable GPIO; alternate functions include IR_OUT, TIM4_CH4, I2C1_SDA, CAN1_TX and SDMMC1_D5. |
| 47 | VSS | power_in | Digital ground pin; all VSS pins must be connected to the board ground and their mutual difference kept within 50 mV. |
| 48 | VDD | power_in | Main digital supply pin, 1.71 V to 3.6 V, with variations between VDD pins kept within 50 mV. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
STM32L4Q5CGT6 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32l4q5cgt6-etched.step/stm32l4q5cgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l4q5cgt6.step/stm32l4q5cgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (285 pp, sha256
614dc3c69063136f, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).