STM32L496VGT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32L496VGT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	FT_l I/O with alternate functions TRACECK, TIM3_ETR, TSC_G7_IO1, LCD_SEG38, FMC_A23, SAI1_MCLK_A.
2	PE3	bidirectional	FT_l I/O with alternate functions TRACED0, TIM3_CH1, TSC_G7_IO2, LCD_SEG39, FMC_A19, SAI1_SD_B.
3	PE4	bidirectional	FT I/O with alternate functions TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, DCMI_D4, FMC_A20, SAI1_FS_A.
4	PE5	bidirectional	FT I/O with alternate functions TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, DCMI_D6, FMC_A21, SAI1_SCK_A.
5	PE6	bidirectional	FT I/O with alternate functions TRACED3, TIM3_CH4, DCMI_D7, FMC_A22, SAI1_SD_A; additional function RTC_TAMP3/WKUP3.
6	VBAT	power_in	Backup domain supply for RTC and backup registers; operating range 1.55 V to 3.6 V.
7	PC13	bidirectional	FT I/O supplied via power switch (3 mA sink limit; output speed max 2 MHz with 30 pF, not for driving LEDs); additional functions RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2.
8	PC14-OSC32_IN	bidirectional	FT I/O supplied via power switch (limited output drive); additional function OSC32_IN for the 32 kHz LSE crystal.
9	PC15-OSC32_OUT	bidirectional	FT I/O supplied via power switch (limited output drive); additional function OSC32_OUT for the 32 kHz LSE crystal.
10	VSS	power_in	Digital ground supply pin.
11	VDD	power_in	Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
12	PH0-OSC_IN	bidirectional	FT I/O (PH0) with additional function OSC_IN for the 4 to 48 MHz crystal oscillator.
13	PH1-OSC_OUT	bidirectional	FT I/O (PH1) with additional function OSC_OUT for the 4 to 48 MHz crystal oscillator.
14	NRST	bidirectional	Bidirectional reset pin with embedded weak pull-up resistor.
15	PC0	bidirectional	FT_fla I/O with LPTIM1_IN1, I2C4_SCL, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX, LCD_SEG18, LPTIM2_IN1; analog ADC123_IN1.
16	PC1	bidirectional	FT_fla I/O with TRACED0, LPTIM1_OUT, I2C4_SDA, SPI2_MOSI, I2C3_SDA, DFSDM1_CKIN4, LPUART1_TX, QUADSPI_BK2_IO0, LCD_SEG19, SAI1_SD_A; analog ADC123_IN2.
17	PC2	bidirectional	FT_la I/O with LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, QUADSPI_BK2_IO1, LCD_SEG20; analog ADC123_IN3.
18	PC3	bidirectional	FT_la I/O with LPTIM1_ETR, SPI2_MOSI, QUADSPI_BK2_IO2, LCD_VLCD, SAI1_SD_A, LPTIM2_ETR; analog ADC123_IN4.
19	VSSA/VREF-	power_in	Analog ground; table name VSSA/VREF-, and VREF- (negative reference) equals VSSA.
20	VREF-	power_in	Negative reference voltage for ADC, equal to VSSA.
21	VREF+	power_in	Positive reference voltage input, also VREFBUF_OUT; ADC VREF+ is 2 V to VDDA when VDDA >= 2 V.
22	VDDA	power_in	Analog supply; 1.62 V min with ADC/COMP, 1.8 V with DAC/OPAMP, 2.4 V with VREFBUF, max 3.6 V.
23	PA0	bidirectional	FT_a I/O with TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI1_EXTCLK, TIM2_ETR; analog OPAMP1_VINP, ADC12_IN5, RTC_TAMP2/WKUP1.
24	PA1	bidirectional	FT_la I/O with TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX, LCD_SEG0, TIM15_CH1N; analog OPAMP1_VINM, ADC12_IN6.
25	PA2	bidirectional	FT_la I/O with TIM2_CH3, TIM5_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG1, SAI2_EXTCLK, TIM15_CH1; analog ADC12_IN7, WKUP4/LSCO.
26	PA3	bidirectional	TT_la I/O with TIM2_CH4, TIM5_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, LCD_SEG2, SAI1_MCLK_A, TIM15_CH2; analog OPAMP1_VOUT, ADC12_IN8.
27	VSS	power_in	Digital ground supply pin.
28	VDD	power_in	Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
29	PA4	bidirectional	TT_a I/O with SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, SAI1_FS_B, LPTIM2_OUT; analog ADC12_IN9, DAC1_OUT1.
30	PA5	bidirectional	TT_a I/O with TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR; analog ADC12_IN10, DAC1_OUT2.
31	PA6	bidirectional	FT_la I/O with TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK, SPI1_MISO, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, LCD_SEG3, TIM16_CH1; analog OPAMP2_VINP, ADC12_IN11.
32	PA7	bidirectional	FT_fla I/O with TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, TIM17_CH1; analog OPAMP2_VINM, ADC12_IN12.
33	PC4	bidirectional	FT_la I/O with USART3_TX, QUADSPI_BK2_IO3, LCD_SEG22; analog COMP1_INM, ADC12_IN13.
34	PC5	bidirectional	FT_la I/O with USART3_RX, LCD_SEG23; analog COMP1_INP, ADC12_IN14, WKUP5.
35	PB0	bidirectional	TT_la I/O with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, LCD_SEG5, COMP1_OUT, SAI1_EXTCLK; analog OPAMP2_VOUT, ADC12_IN15.
36	PB1	bidirectional	FT_la I/O with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1; analog COMP1_INM, ADC12_IN16.
37	PB2	bidirectional	FT_la I/O with RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0, LCD_VLCD; analog COMP1_INP.
38	PE7	bidirectional	FT I/O with TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B.
39	PE8	bidirectional	FT I/O with TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B.
40	PE9	bidirectional	FT I/O with TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B.
41	PE10	bidirectional	FT I/O with TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B.
42	PE11	bidirectional	FT I/O with TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, QUADSPI_BK1_NCS, FMC_D8.
43	PE12	bidirectional	FT I/O with TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9.
44	PE13	bidirectional	FT I/O with TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10.
45	PE14	bidirectional	FT I/O with TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11.
46	PE15	bidirectional	FT I/O with TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12.
47	PB10	bidirectional	FT_fl I/O with TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A.
48	PB11	bidirectional	FT_fl I/O with TIM2_CH4, I2C4_SDA, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG11, COMP2_OUT.
49	VSS	power_in	Digital ground supply pin.
50	VDD	power_in	Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
51	PB12	bidirectional	FT_l I/O with TIM1_BKIN, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN2_RX, LCD_SEG12, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN.
52	PB13	bidirectional	FT_fl I/O with TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN2_TX, LCD_SEG13, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N.
53	PB14	bidirectional	FT_fl I/O with TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1.
54	PB15	bidirectional	FT_l I/O with RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2.
55	PD8	bidirectional	FT_l I/O with USART3_TX, DCMI_HSYNC, LCD_SEG28, FMC_D13.
56	PD9	bidirectional	FT_l I/O with USART3_RX, DCMI_PIXCLK, LCD_SEG29, FMC_D14, SAI2_MCLK_A.
57	PD10	bidirectional	FT_l I/O with USART3_CK, TSC_G6_IO1, LCD_SEG30, FMC_D15, SAI2_SCK_A.
58	PD11	bidirectional	FT_l I/O with I2C4_SMBA, USART3_CTS, TSC_G6_IO2, LCD_SEG31, FMC_A16, SAI2_SD_A, LPTIM2_ETR.
59	PD12	bidirectional	FT_fl I/O with TIM4_CH1, I2C4_SCL, USART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, FMC_A17, SAI2_FS_A, LPTIM2_IN1.
60	PD13	bidirectional	FT_fl I/O with TIM4_CH2, I2C4_SDA, TSC_G6_IO4, LCD_SEG33, FMC_A18, LPTIM2_OUT.
61	PD14	bidirectional	FT_l I/O with TIM4_CH3, LCD_SEG34, FMC_D0.
62	PD15	bidirectional	FT_l I/O with TIM4_CH4, LCD_SEG35, FMC_D1.
63	PC6	bidirectional	FT_l I/O with TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, DCMI_D0, LCD_SEG24, SDMMC1_D6, SAI2_MCLK_A.
64	PC7	bidirectional	FT_l I/O with TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, DCMI_D1, LCD_SEG25, SDMMC1_D7, SAI2_MCLK_B.
65	PC8	bidirectional	FT_l I/O with TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2, LCD_SEG26, SDMMC1_D0.
66	PC9	bidirectional	FT_fl I/O with TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3, I2C3_SDA, TSC_G4_IO4, OTG_FS_NOE, LCD_SEG27, SDMMC1_D1, SAI2_EXTCLK.
67	PA8	bidirectional	FT_l I/O with MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF, LCD_COM0, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT.
68	PA9	bidirectional	FT_lu I/O with TIM1_CH2, SPI2_SCK, DCMI_D0, USART1_TX, LCD_COM1, SAI1_FS_A, TIM15_BKIN; additional function OTG_FS_VBUS.
69	PA10	bidirectional	FT_lu I/O with TIM1_CH3, DCMI_D1, USART1_RX, OTG_FS_ID, LCD_COM2, SAI1_SD_A, TIM17_BKIN.
70	PA11	bidirectional	FT_u I/O with TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, CAN1_RX, OTG_FS_DM.
71	PA12	bidirectional	FT_u I/O with TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, OTG_FS_DP.
72	PA13	bidirectional	FT I/O, JTMS/SWDIO after reset (internal pull-up active), with IR_OUT, OTG_FS_NOE, SWPMI1_TX, SAI1_SD_B.
73	VDDUSB	power_in	USB supply; 3.0 V to 3.6 V when USB is used, 0 to 3.6 V when not used.
74	VSS	power_in	Digital ground supply pin.
75	VDD	power_in	Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
76	PA14	bidirectional	FT I/O, JTCK/SWCLK after reset (internal pull-down active), with LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SWPMI1_RX, SAI1_FS_B.
77	PA15	bidirectional	FT_l I/O, JTDI after reset (internal pull-up active), with TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, TSC_G3_IO1, LCD_SEG17, SWPMI1_SUSPEND, SAI2_FS_B.
78	PC10	bidirectional	FT_l I/O with TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, DCMI_D8, LCD_COM4/SEG28/SEG40, SDMMC1_D2, SAI2_SCK_B.
79	PC11	bidirectional	FT_l I/O with QUADSPI_BK2_NCS, SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, DCMI_D4, LCD_COM5/SEG29/SEG41, SDMMC1_D3, SAI2_MCLK_B.
80	PC12	bidirectional	FT_l I/O with TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9, LCD_COM6/SEG30/SEG42, SDMMC1_CK, SAI2_SD_B.
81	PD0	bidirectional	FT I/O with SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2.
82	PD1	bidirectional	FT I/O with SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3.
83	PD2	bidirectional	FT_l I/O with TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11, LCD_COM7/SEG31/SEG43, SDMMC1_CMD.
84	PD3	bidirectional	FT I/O with SPI2_SCK, DCMI_D5, SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, QUADSPI_BK2_NCS, FMC_CLK.
85	PD4	bidirectional	FT I/O with SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, QUADSPI_BK2_IO0, FMC_NOE.
86	PD5	bidirectional	FT I/O with USART2_TX, QUADSPI_BK2_IO1, FMC_NWE.
87	PD6	bidirectional	FT I/O with DCMI_D10, QUADSPI_BK2_IO1, DFSDM1_DATIN1, USART2_RX, QUADSPI_BK2_IO2, FMC_NWAIT, SAI1_SD_A.
88	PD7	bidirectional	FT I/O with DFSDM1_CKIN1, USART2_CK, QUADSPI_BK2_IO3, FMC_NE1.
89	PB3	bidirectional	FT_la I/O, JTDO/TRACESWO after reset, with TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, OTG_FS_CRS_SYNC, LCD_SEG7, SAI1_SCK_B; analog COMP2_INM.
90	PB4	bidirectional	FT_fla I/O, NJTRST after reset (internal pull-up active), with TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, DCMI_D12, LCD_SEG8, SAI1_MCLK_B, TIM17_BKIN; analog COMP2_INP.
91	PB5	bidirectional	FT_la I/O with LPTIM1_IN1, TIM3_CH2, CAN2_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, DCMI_D10, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN.
92	PB6	bidirectional	FT_fa I/O with LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, I2C4_SCL, DFSDM1_DATIN5, USART1_TX, CAN2_TX, TSC_G2_IO3, DCMI_D5, SAI1_FS_B, TIM16_CH1N; analog COMP2_INP.
93	PB7	bidirectional	FT_fla I/O with LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, I2C4_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, DCMI_VSYNC, LCD_SEG21, FMC_NL, TIM17_CH1N; analog COMP2_INM, PVD_IN.
94	PH3-BOOT0	input	FT pin PH3 / BOOT0 boot mode selection; BOOT0 input voltage up to 9 V.
95	PB8	bidirectional	FT_fl I/O with TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, DCMI_D6, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1.
96	PB9	bidirectional	FT_fl I/O with IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, DCMI_D7, LCD_COM3, SDMMC1_D5, SAI1_FS_A, TIM17_CH1.
97	PE0	bidirectional	FT_l I/O with TIM4_ETR, DCMI_D2, LCD_SEG36, FMC_NBL0, TIM16_CH1.
98	PE1	bidirectional	FT_l I/O with DCMI_D3, LCD_SEG37, FMC_NBL1, TIM17_CH1.
99	VSS	power_in	Digital ground supply pin.
100	VDD	power_in	Digital supply pin; standard operating voltage 1.71 V to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

CAD (KiCad official)

Symbol: STM32L496VGT6
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: stm32l496vgt6-etched.step / stm32l496vgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l496vgt6.step / stm32l496vgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (281 pp, sha256 f285c0ab8ccf5d95, retrieved 2026-10-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# STM32L496VGT6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32L496VGT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | FT_l I/O with alternate functions TRACECK, TIM3_ETR, TSC_G7_IO1, LCD_SEG38, FMC_A23, SAI1_MCLK_A. |
| 2 | PE3 | bidirectional | FT_l I/O with alternate functions TRACED0, TIM3_CH1, TSC_G7_IO2, LCD_SEG39, FMC_A19, SAI1_SD_B. |
| 3 | PE4 | bidirectional | FT I/O with alternate functions TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, DCMI_D4, FMC_A20, SAI1_FS_A. |
| 4 | PE5 | bidirectional | FT I/O with alternate functions TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, DCMI_D6, FMC_A21, SAI1_SCK_A. |
| 5 | PE6 | bidirectional | FT I/O with alternate functions TRACED3, TIM3_CH4, DCMI_D7, FMC_A22, SAI1_SD_A; additional function RTC_TAMP3/WKUP3. |
| 6 | VBAT | power_in | Backup domain supply for RTC and backup registers; operating range 1.55 V to 3.6 V. |
| 7 | PC13 | bidirectional | FT I/O supplied via power switch (3 mA sink limit; output speed max 2 MHz with 30 pF, not for driving LEDs); additional functions RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2. |
| 8 | PC14-OSC32_IN | bidirectional | FT I/O supplied via power switch (limited output drive); additional function OSC32_IN for the 32 kHz LSE crystal. |
| 9 | PC15-OSC32_OUT | bidirectional | FT I/O supplied via power switch (limited output drive); additional function OSC32_OUT for the 32 kHz LSE crystal. |
| 10 | VSS | power_in | Digital ground supply pin. |
| 11 | VDD | power_in | Digital supply pin; standard operating voltage 1.71 V to 3.6 V. |
| 12 | PH0-OSC_IN | bidirectional | FT I/O (PH0) with additional function OSC_IN for the 4 to 48 MHz crystal oscillator. |
| 13 | PH1-OSC_OUT | bidirectional | FT I/O (PH1) with additional function OSC_OUT for the 4 to 48 MHz crystal oscillator. |
| 14 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 15 | PC0 | bidirectional | FT_fla I/O with LPTIM1_IN1, I2C4_SCL, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX, LCD_SEG18, LPTIM2_IN1; analog ADC123_IN1. |
| 16 | PC1 | bidirectional | FT_fla I/O with TRACED0, LPTIM1_OUT, I2C4_SDA, SPI2_MOSI, I2C3_SDA, DFSDM1_CKIN4, LPUART1_TX, QUADSPI_BK2_IO0, LCD_SEG19, SAI1_SD_A; analog ADC123_IN2. |
| 17 | PC2 | bidirectional | FT_la I/O with LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, QUADSPI_BK2_IO1, LCD_SEG20; analog ADC123_IN3. |
| 18 | PC3 | bidirectional | FT_la I/O with LPTIM1_ETR, SPI2_MOSI, QUADSPI_BK2_IO2, LCD_VLCD, SAI1_SD_A, LPTIM2_ETR; analog ADC123_IN4. |
| 19 | VSSA/VREF- | power_in | Analog ground; table name VSSA/VREF-, and VREF- (negative reference) equals VSSA. |
| 20 | VREF- | power_in | Negative reference voltage for ADC, equal to VSSA. |
| 21 | VREF+ | power_in | Positive reference voltage input, also VREFBUF_OUT; ADC VREF+ is 2 V to VDDA when VDDA >= 2 V. |
| 22 | VDDA | power_in | Analog supply; 1.62 V min with ADC/COMP, 1.8 V with DAC/OPAMP, 2.4 V with VREFBUF, max 3.6 V. |
| 23 | PA0 | bidirectional | FT_a I/O with TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI1_EXTCLK, TIM2_ETR; analog OPAMP1_VINP, ADC12_IN5, RTC_TAMP2/WKUP1. |
| 24 | PA1 | bidirectional | FT_la I/O with TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX, LCD_SEG0, TIM15_CH1N; analog OPAMP1_VINM, ADC12_IN6. |
| 25 | PA2 | bidirectional | FT_la I/O with TIM2_CH3, TIM5_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG1, SAI2_EXTCLK, TIM15_CH1; analog ADC12_IN7, WKUP4/LSCO. |
| 26 | PA3 | bidirectional | TT_la I/O with TIM2_CH4, TIM5_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, LCD_SEG2, SAI1_MCLK_A, TIM15_CH2; analog OPAMP1_VOUT, ADC12_IN8. |
| 27 | VSS | power_in | Digital ground supply pin. |
| 28 | VDD | power_in | Digital supply pin; standard operating voltage 1.71 V to 3.6 V. |
| 29 | PA4 | bidirectional | TT_a I/O with SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, SAI1_FS_B, LPTIM2_OUT; analog ADC12_IN9, DAC1_OUT1. |
| 30 | PA5 | bidirectional | TT_a I/O with TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR; analog ADC12_IN10, DAC1_OUT2. |
| 31 | PA6 | bidirectional | FT_la I/O with TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK, SPI1_MISO, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, LCD_SEG3, TIM16_CH1; analog OPAMP2_VINP, ADC12_IN11. |
| 32 | PA7 | bidirectional | FT_fla I/O with TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, TIM17_CH1; analog OPAMP2_VINM, ADC12_IN12. |
| 33 | PC4 | bidirectional | FT_la I/O with USART3_TX, QUADSPI_BK2_IO3, LCD_SEG22; analog COMP1_INM, ADC12_IN13. |
| 34 | PC5 | bidirectional | FT_la I/O with USART3_RX, LCD_SEG23; analog COMP1_INP, ADC12_IN14, WKUP5. |
| 35 | PB0 | bidirectional | TT_la I/O with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, LCD_SEG5, COMP1_OUT, SAI1_EXTCLK; analog OPAMP2_VOUT, ADC12_IN15. |
| 36 | PB1 | bidirectional | FT_la I/O with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1; analog COMP1_INM, ADC12_IN16. |
| 37 | PB2 | bidirectional | FT_la I/O with RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0, LCD_VLCD; analog COMP1_INP. |
| 38 | PE7 | bidirectional | FT I/O with TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B. |
| 39 | PE8 | bidirectional | FT I/O with TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B. |
| 40 | PE9 | bidirectional | FT I/O with TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B. |
| 41 | PE10 | bidirectional | FT I/O with TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B. |
| 42 | PE11 | bidirectional | FT I/O with TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, QUADSPI_BK1_NCS, FMC_D8. |
| 43 | PE12 | bidirectional | FT I/O with TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9. |
| 44 | PE13 | bidirectional | FT I/O with TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10. |
| 45 | PE14 | bidirectional | FT I/O with TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11. |
| 46 | PE15 | bidirectional | FT I/O with TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12. |
| 47 | PB10 | bidirectional | FT_fl I/O with TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A. |
| 48 | PB11 | bidirectional | FT_fl I/O with TIM2_CH4, I2C4_SDA, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG11, COMP2_OUT. |
| 49 | VSS | power_in | Digital ground supply pin. |
| 50 | VDD | power_in | Digital supply pin; standard operating voltage 1.71 V to 3.6 V. |
| 51 | PB12 | bidirectional | FT_l I/O with TIM1_BKIN, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN2_RX, LCD_SEG12, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN. |
| 52 | PB13 | bidirectional | FT_fl I/O with TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN2_TX, LCD_SEG13, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N. |
| 53 | PB14 | bidirectional | FT_fl I/O with TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1. |
| 54 | PB15 | bidirectional | FT_l I/O with RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2. |
| 55 | PD8 | bidirectional | FT_l I/O with USART3_TX, DCMI_HSYNC, LCD_SEG28, FMC_D13. |
| 56 | PD9 | bidirectional | FT_l I/O with USART3_RX, DCMI_PIXCLK, LCD_SEG29, FMC_D14, SAI2_MCLK_A. |
| 57 | PD10 | bidirectional | FT_l I/O with USART3_CK, TSC_G6_IO1, LCD_SEG30, FMC_D15, SAI2_SCK_A. |
| 58 | PD11 | bidirectional | FT_l I/O with I2C4_SMBA, USART3_CTS, TSC_G6_IO2, LCD_SEG31, FMC_A16, SAI2_SD_A, LPTIM2_ETR. |
| 59 | PD12 | bidirectional | FT_fl I/O with TIM4_CH1, I2C4_SCL, USART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, FMC_A17, SAI2_FS_A, LPTIM2_IN1. |
| 60 | PD13 | bidirectional | FT_fl I/O with TIM4_CH2, I2C4_SDA, TSC_G6_IO4, LCD_SEG33, FMC_A18, LPTIM2_OUT. |
| 61 | PD14 | bidirectional | FT_l I/O with TIM4_CH3, LCD_SEG34, FMC_D0. |
| 62 | PD15 | bidirectional | FT_l I/O with TIM4_CH4, LCD_SEG35, FMC_D1. |
| 63 | PC6 | bidirectional | FT_l I/O with TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, DCMI_D0, LCD_SEG24, SDMMC1_D6, SAI2_MCLK_A. |
| 64 | PC7 | bidirectional | FT_l I/O with TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, DCMI_D1, LCD_SEG25, SDMMC1_D7, SAI2_MCLK_B. |
| 65 | PC8 | bidirectional | FT_l I/O with TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2, LCD_SEG26, SDMMC1_D0. |
| 66 | PC9 | bidirectional | FT_fl I/O with TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3, I2C3_SDA, TSC_G4_IO4, OTG_FS_NOE, LCD_SEG27, SDMMC1_D1, SAI2_EXTCLK. |
| 67 | PA8 | bidirectional | FT_l I/O with MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF, LCD_COM0, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT. |
| 68 | PA9 | bidirectional | FT_lu I/O with TIM1_CH2, SPI2_SCK, DCMI_D0, USART1_TX, LCD_COM1, SAI1_FS_A, TIM15_BKIN; additional function OTG_FS_VBUS. |
| 69 | PA10 | bidirectional | FT_lu I/O with TIM1_CH3, DCMI_D1, USART1_RX, OTG_FS_ID, LCD_COM2, SAI1_SD_A, TIM17_BKIN. |
| 70 | PA11 | bidirectional | FT_u I/O with TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, CAN1_RX, OTG_FS_DM. |
| 71 | PA12 | bidirectional | FT_u I/O with TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, OTG_FS_DP. |
| 72 | PA13 | bidirectional | FT I/O, JTMS/SWDIO after reset (internal pull-up active), with IR_OUT, OTG_FS_NOE, SWPMI1_TX, SAI1_SD_B. |
| 73 | VDDUSB | power_in | USB supply; 3.0 V to 3.6 V when USB is used, 0 to 3.6 V when not used. |
| 74 | VSS | power_in | Digital ground supply pin. |
| 75 | VDD | power_in | Digital supply pin; standard operating voltage 1.71 V to 3.6 V. |
| 76 | PA14 | bidirectional | FT I/O, JTCK/SWCLK after reset (internal pull-down active), with LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SWPMI1_RX, SAI1_FS_B. |
| 77 | PA15 | bidirectional | FT_l I/O, JTDI after reset (internal pull-up active), with TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, TSC_G3_IO1, LCD_SEG17, SWPMI1_SUSPEND, SAI2_FS_B. |
| 78 | PC10 | bidirectional | FT_l I/O with TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, DCMI_D8, LCD_COM4/SEG28/SEG40, SDMMC1_D2, SAI2_SCK_B. |
| 79 | PC11 | bidirectional | FT_l I/O with QUADSPI_BK2_NCS, SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, DCMI_D4, LCD_COM5/SEG29/SEG41, SDMMC1_D3, SAI2_MCLK_B. |
| 80 | PC12 | bidirectional | FT_l I/O with TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9, LCD_COM6/SEG30/SEG42, SDMMC1_CK, SAI2_SD_B. |
| 81 | PD0 | bidirectional | FT I/O with SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2. |
| 82 | PD1 | bidirectional | FT I/O with SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3. |
| 83 | PD2 | bidirectional | FT_l I/O with TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11, LCD_COM7/SEG31/SEG43, SDMMC1_CMD. |
| 84 | PD3 | bidirectional | FT I/O with SPI2_SCK, DCMI_D5, SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, QUADSPI_BK2_NCS, FMC_CLK. |
| 85 | PD4 | bidirectional | FT I/O with SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, QUADSPI_BK2_IO0, FMC_NOE. |
| 86 | PD5 | bidirectional | FT I/O with USART2_TX, QUADSPI_BK2_IO1, FMC_NWE. |
| 87 | PD6 | bidirectional | FT I/O with DCMI_D10, QUADSPI_BK2_IO1, DFSDM1_DATIN1, USART2_RX, QUADSPI_BK2_IO2, FMC_NWAIT, SAI1_SD_A. |
| 88 | PD7 | bidirectional | FT I/O with DFSDM1_CKIN1, USART2_CK, QUADSPI_BK2_IO3, FMC_NE1. |
| 89 | PB3 | bidirectional | FT_la I/O, JTDO/TRACESWO after reset, with TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, OTG_FS_CRS_SYNC, LCD_SEG7, SAI1_SCK_B; analog COMP2_INM. |
| 90 | PB4 | bidirectional | FT_fla I/O, NJTRST after reset (internal pull-up active), with TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, DCMI_D12, LCD_SEG8, SAI1_MCLK_B, TIM17_BKIN; analog COMP2_INP. |
| 91 | PB5 | bidirectional | FT_la I/O with LPTIM1_IN1, TIM3_CH2, CAN2_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, DCMI_D10, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN. |
| 92 | PB6 | bidirectional | FT_fa I/O with LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, I2C4_SCL, DFSDM1_DATIN5, USART1_TX, CAN2_TX, TSC_G2_IO3, DCMI_D5, SAI1_FS_B, TIM16_CH1N; analog COMP2_INP. |
| 93 | PB7 | bidirectional | FT_fla I/O with LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, I2C4_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, DCMI_VSYNC, LCD_SEG21, FMC_NL, TIM17_CH1N; analog COMP2_INM, PVD_IN. |
| 94 | PH3-BOOT0 | input | FT pin PH3 / BOOT0 boot mode selection; BOOT0 input voltage up to 9 V. |
| 95 | PB8 | bidirectional | FT_fl I/O with TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, DCMI_D6, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1. |
| 96 | PB9 | bidirectional | FT_fl I/O with IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, DCMI_D7, LCD_COM3, SDMMC1_D5, SAI1_FS_A, TIM17_CH1. |
| 97 | PE0 | bidirectional | FT_l I/O with TIM4_ETR, DCMI_D2, LCD_SEG36, FMC_NBL0, TIM16_CH1. |
| 98 | PE1 | bidirectional | FT_l I/O with DCMI_D3, LCD_SEG37, FMC_NBL1, TIM17_CH1. |
| 99 | VSS | power_in | Digital ground supply pin. |
| 100 | VDD | power_in | Digital supply pin; standard operating voltage 1.71 V to 3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## CAD (KiCad official)

- Symbol: `STM32L496VGT6`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `stm32l496vgt6-etched.step` / `stm32l496vgt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32l496vgt6.step` / `stm32l496vgt6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885254472286208) (281 pp, sha256 `f285c0ab8ccf5d95`, retrieved 2026-10-05, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32l496vgt6-datasheet.pdf)