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STM32L496RET6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32l496ret6factory-2.0.0extractor-text
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STM32L496RET6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32L496RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply for the RTC and 32x32-bit backup registers, operating from 1.55 V to 3.6 V.
2 PC13 bidirectional 5 V-tolerant GPIO (FT) supplied through the power switch, which sinks only 3 mA, so output speed is limited to 2 MHz with 30 pF and it must not source current to drive LEDs; also RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2.
3 PC14-OSC32_IN bidirectional 5 V-tolerant GPIO (FT) supplied through the power switch with the same 3 mA sink, 2 MHz / 30 pF and no-current-source limits, and used as the 32 kHz LSE oscillator input OSC32_IN.
4 PC15-OSC32_OUT bidirectional 5 V-tolerant GPIO (FT) supplied through the power switch with the same 3 mA sink, 2 MHz / 30 pF and no-current-source limits, and used as the 32 kHz LSE oscillator output OSC32_OUT.
5 PH0-OSC_IN bidirectional 5 V-tolerant GPIO (FT) that also serves as the OSC_IN external oscillator input.
6 PH1-OSC_OUT bidirectional 5 V-tolerant GPIO (FT) that also serves as the OSC_OUT external oscillator output.
7 NRST bidirectional Bidirectional reset pin with an embedded weak pull-up resistor.
8 PC0 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fla) with LCD function supplied by VLCD and analog switch supplied by VDDA; ADC123_IN1 analog input, also LPUART1_RX, LPTIM1_IN1, I2C3_SCL and I2C4_SCL.
9 PC1 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fla) with LCD function supplied by VLCD and analog switch supplied by VDDA; ADC123_IN2 analog input, also LPUART1_TX, SPI2_MOSI, I2C3_SDA and TRACED0.
10 PC2 bidirectional 5 V-tolerant I/O (FT_la) with LCD function supplied by VLCD and analog switch supplied by VDDA; ADC123_IN3 analog input, also SPI2_MISO, LPTIM1_IN2 and DFSDM1_CKOUT.
11 PC3 bidirectional 5 V-tolerant I/O (FT_la) with LCD function supplied by VLCD and analog switch supplied by VDDA; ADC123_IN4 analog input, also LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A and LPTIM2_ETR.
12 VSSA/VREF- power_in Analog ground and negative reference voltage, to be connected to VSSA; VREF- must be within the ground-pin variation limit of 50 mV.
13 VDDA/VREF+ power_in Analog supply (1.62 V to 3.6 V with ADC or COMP, 1.8 V with DAC or OPAMP, 2.4 V with VREFBUF) and positive ADC reference, where VREF+ must be at least 2 V when VDDA is 2 V or higher and may exceed VDDA by no more than 0.4 V.
14 PA0 bidirectional 5 V-tolerant I/O (FT_a) with analog switch function supplied by VDDA; OPAMP1_VINP, ADC12_IN5 and RTC_TAMP2/WKUP1 analog functions, also TIM2_CH1, TIM8_ETR and USART2_CTS.
15 PA1 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; OPAMP1_VINM and ADC12_IN6 analog functions, also TIM2_CH2, SPI1_SCK, I2C1_SMBA and USART2_RTS_DE.
16 PA2 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; ADC12_IN7 and WKUP4/LSCO analog functions, also TIM2_CH3, USART2_TX, LPUART1_TX and QUADSPI_BK1_NCS.
17 PA3 bidirectional 3.6 V-tolerant I/O (TT_la) with LCD and analog switch functions; OPAMP1_VOUT and ADC12_IN8 analog functions, also TIM2_CH4, USART2_RX and LPUART1_RX.
18 VSS power_in Ground pin; must be connected to the common ground with a difference of no more than 50 mV from the other VSS pins.
19 VDD power_in Main supply pin, 1.71 V to 3.6 V, with no more than 50 mV variation between VDD pins.
20 PA4 bidirectional 3.6 V-tolerant I/O (TT_a) with analog switch function supplied by VDDA; ADC12_IN9 and DAC1_OUT1 analog functions, also SPI1_NSS, SPI3_NSS, USART2_CK and DCMI_HSYNC.
21 PA5 bidirectional 3.6 V-tolerant I/O (TT_a) with analog switch function supplied by VDDA; ADC12_IN10 and DAC1_OUT2 analog functions, also TIM2_CH1, TIM2_ETR, SPI1_SCK and LPTIM2_ETR.
22 PA6 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; OPAMP2_VINP and ADC12_IN11 analog functions, also TIM1_BKIN, SPI1_MISO, LPUART1_CTS and QUADSPI_BK1_IO3.
23 PA7 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fla) with LCD and analog switch functions; OPAMP2_VINM and ADC12_IN12 analog functions, also TIM1_CH1N, TIM3_CH2, I2C3_SCL and SPI1_MOSI.
24 PC4 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; COMP1_INM and ADC12_IN13 analog functions, also USART3_TX, QUADSPI_BK2_IO3 and LCD_SEG22.
25 PC5 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; COMP1_INP, ADC12_IN14 and WKUP5 analog functions, also USART3_RX and LCD_SEG23.
26 PB0 bidirectional 3.6 V-tolerant I/O (TT_la) with LCD and analog switch functions; OPAMP2_VOUT and ADC12_IN15 analog functions, also TIM1_CH2N, TIM3_CH3, SPI1_NSS and COMP1_OUT.
27 PB1 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; COMP1_INM and ADC12_IN16 analog functions, also TIM1_CH3N, TIM3_CH4, LPUART1_RTS_DE and LPTIM2_IN1.
28 PB2 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; COMP1_INP analog function, also RTC_OUT, LPTIM1_OUT, I2C3_SMBA and LCD_VLCD.
29 PB10 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fl) with LCD function supplied by VLCD; also I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC and COMP1_OUT.
30 PB11 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fl) with LCD function supplied by VLCD; also I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS and COMP2_OUT.
31 VSS power_in Ground pin; must be connected to the common ground with a difference of no more than 50 mV from the other VSS pins.
32 VDD power_in Main supply pin, 1.71 V to 3.6 V, with no more than 50 mV variation between VDD pins.
33 PB12 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also TIM1_BKIN, I2C2_SMBA, SPI2_NSS, USART3_CK, CAN2_RX and TSC_G1_IO1.
34 PB13 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fl) with LCD function supplied by VLCD; also TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS and CAN2_TX.
35 PB14 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fl) with LCD function supplied by VLCD; also TIM1_CH2N, I2C2_SDA, SPI2_MISO and USART3_RTS_DE.
36 PB15 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also RTC_REFIN, TIM1_CH3N, SPI2_MOSI and LCD_SEG15.
37 PC6 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, DCMI_D0 and SDMMC1_D6.
38 PC7 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, DCMI_D1 and SDMMC1_D7.
39 PC8 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2 and SDMMC1_D0.
40 PC9 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fl) with LCD function supplied by VLCD; also TIM8_BKIN2, TIM3_CH4, TIM8_CH4, I2C3_SDA, DCMI_D3 and SDMMC1_D1.
41 PA8 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF and LCD_COM0.
42 PA9 bidirectional 5 V-tolerant I/O (FT_lu) with LCD function supplied by VLCD and USB function supplied by VDDUSB; OTG_FS_VBUS, also TIM1_CH2, SPI2_SCK, DCMI_D0 and USART1_TX.
43 PA10 bidirectional 5 V-tolerant I/O (FT_lu) with LCD function supplied by VLCD and USB function supplied by VDDUSB; OTG_FS_ID, also TIM1_CH3, DCMI_D1, USART1_RX and SAI1_SD_A.
44 PA11 bidirectional 5 V-tolerant I/O (FT_u) with USB function supplied by VDDUSB; OTG_FS_DM, also TIM1_CH4, SPI1_MISO, USART1_CTS and CAN1_RX.
45 PA12 bidirectional 5 V-tolerant I/O (FT_u) with USB function supplied by VDDUSB; OTG_FS_DP, also TIM1_ETR, SPI1_MOSI, USART1_RTS_DE and CAN1_TX.
46 PA13 bidirectional 5 V-tolerant I/O (FT) that after reset is the JTMS/SWDIO debug function with the internal pull-up activated; also IR_OUT, OTG_FS_NOE and SWPMI1_TX.
47 VSS power_in Ground pin; must be connected to the common ground with a difference of no more than 50 mV from the other VSS pins.
48 VDDUSB power_in USB supply, 3.0 V to 3.6 V when USB is used (0 V to 3.6 V when USB is not used).
49 PA14 bidirectional 5 V-tolerant I/O (FT) that after reset is the JTCK/SWCLK debug function with the internal pull-down activated; also LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA and SAI1_FS_B.
50 PA15 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD that after reset is the JTDI debug function with the internal pull-up activated; also TIM2_CH1, USART2_RX, SPI1_NSS and SPI3_NSS.
51 PC10 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also TRACED1, SPI3_SCK, USART3_TX, UART4_TX, DCMI_D8 and SDMMC1_D2.
52 PC11 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also QUADSPI_BK2_NCS, SPI3_MISO, USART3_RX, UART4_RX, DCMI_D4 and SDMMC1_D3.
53 PC12 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, DCMI_D9 and SDMMC1_CK.
54 PD2 bidirectional 5 V-tolerant I/O (FT_l) with LCD function supplied by VLCD; also TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC and SDMMC1_CMD.
55 PB3 bidirectional 5 V-tolerant I/O (FT_la) that after reset is the JTDO/TRACESWO debug function, with LCD and analog switch functions; COMP2_INM analog input, also TIM2_CH2, SPI1_SCK, SPI3_SCK and USART1_RTS_DE.
56 PB4 bidirectional 5 V-tolerant I/O (FT_fla) that after reset is the NJTRST debug function with the internal pull-up activated; COMP2_INP analog input, also TIM3_CH1, I2C3_SDA, SPI1_MISO and USART1_CTS.
57 PB5 bidirectional 5 V-tolerant I/O (FT_la) with LCD and analog switch functions; COMP2_OUT, also LPTIM1_IN1, TIM3_CH2, CAN2_RX, I2C1_SMBA, SPI1_MOSI and DCMI_D10.
58 PB6 bidirectional 5 V-tolerant I/O (FT_fa) with analog switch function supplied by VDDA; COMP2_INP analog input, also LPTIM1_ETR, TIM4_CH1, I2C1_SCL, I2C4_SCL and USART1_TX.
59 PB7 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fla) with LCD and analog switch functions; COMP2_INM and PVD_IN analog functions, also LPTIM1_IN2, TIM4_CH2, I2C1_SDA, I2C4_SDA and USART1_RX.
60 PH3-BOOT0 bidirectional 5 V-tolerant I/O (FT) that is also the BOOT0 boot-configuration input, whose input voltage range is 0 to 9 V.
61 PB8 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fl) with LCD function supplied by VLCD; also TIM4_CH3, I2C1_SCL, CAN1_RX, DCMI_D6, LCD_SEG16 and SDMMC1_D4.
62 PB9 bidirectional Fm+-capable 5 V-tolerant I/O (FT_fl) with LCD function supplied by VLCD; also IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, CAN1_TX and LCD_COM3.
63 VSS power_in Ground pin; must be connected to the common ground with a difference of no more than 50 mV from the other VSS pins.
64 VDD power_in Main supply pin, 1.71 V to 3.6 V, with no more than 50 mV variation between VDD pins.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32L496RET6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32l496ret6-etched.step / stm32l496ret6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l496ret6.step / stm32l496ret6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (284 pp, sha256 7a132a25c182f83e, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF