component

STM32L486RGT6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32l486rgt6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers stm32l486rgt6: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/stm32l486rgt6 · Ray 1d ago
stm32l486rgt6-etched.glb stm32l486rgt6: factory component page (tier=lcsc) · Ray 1d ago
stm32l486rgt6-etched.step stm32l486rgt6: factory component page (tier=lcsc) · Ray 1d ago
stm32l486rgt6-hero.glb stm32l486rgt6: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
stm32l486rgt6-hero.overlay.json Publish 0.1.0 · Ray 1d ago
stm32l486rgt6.glb Publish 0.1.0 · Ray 1d ago
stm32l486rgt6.kicad_mod Publish 0.1.0 · Ray 1d ago
stm32l486rgt6.kicad_sym Publish 0.1.0 · Ray 1d ago
stm32l486rgt6.lbr Publish 0.1.0 · Ray 1d ago
stm32l486rgt6.step Publish 0.1.0 · Ray 1d ago

STM32L486RGT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32L486RGT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply for the RTC and 32x32-bit backup registers, with a backup operating voltage of 1.55 V to 3.6 V.
2 PC13 bidirectional FT I/O supplied through the power switch, which sinks or sources only 3 mA, so output speed is limited to 2 MHz with 30 pF maximum load and it must not be used as a current source.
3 PC14-OSC32_IN (PC14) bidirectional FT I/O supplied through the power switch (3 mA limit, 2 MHz / 30 pF output limit) that doubles as the 32 kHz LSE oscillator input OSC32_IN.
4 PC15-OSC32_OUT (PC15) bidirectional FT I/O supplied through the power switch (3 mA limit, 2 MHz / 30 pF output limit) that doubles as the 32 kHz LSE oscillator output OSC32_OUT.
5 PH0-OSC_IN (PH0) bidirectional FT I/O that doubles as the high-speed external oscillator input OSC_IN (EVENTOUT alternate function also available).
6 PH1-OSC_OUT (PH1) bidirectional FT I/O that doubles as the high-speed external oscillator output OSC_OUT (EVENTOUT alternate function also available).
7 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
8 PC0 bidirectional FT_fla I/O (Fm+ capable, LCD function supplied by VLCD, analog switch supplied by VDDA) with ADC123_IN1 analog input, plus LPTIM1_IN1, I2C3_SCL, LPUART1_RX, LCD_SEG18 and LPTIM2_IN1.
9 PC1 bidirectional FT_fla I/O (Fm+ capable, LCD function supplied by VLCD, analog switch supplied by VDDA) with ADC123_IN2 analog input, plus LPTIM1_OUT, I2C3_SDA, LPUART1_TX and LCD_SEG19.
10 PC2 bidirectional FT_la I/O (LCD function supplied by VLCD, analog switch supplied by VDDA) with ADC123_IN3 analog input, plus LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT and LCD_SEG20.
11 PC3 bidirectional FT_a I/O (analog switch supplied by VDDA) with ADC123_IN4 analog input, plus LPTIM1_ETR, SPI2_MOSI, LCD_VLCD and SAI1_SD_A.
12 VSSA/VREF- power_in Analog ground pin, which also serves as the ADC negative reference VREF- and must be within 50 mV of the other ground pins.
13 VDDA/VREF+ power_in Analog supply pin (1.62 V to 3.6 V when ADC or COMP is used) that also serves as the ADC positive reference VREF+ on this package.
14 PA0 bidirectional FT_a I/O (analog switch supplied by VDDA) with ADC12_IN5 and OPAMP1_VINP inputs, plus TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX and RTC_TAMP2/WKUP1.
15 PA1 bidirectional FT_la I/O (analog switch supplied by VDDA) with ADC12_IN6 and OPAMP1_VINM inputs, plus TIM2_CH2, TIM5_CH2, USART2_RTS_DE, UART4_RX and LCD_SEG0.
16 PA2 bidirectional FT_la I/O (analog switch supplied by VDDA) with ADC12_IN7 analog input, plus TIM2_CH3, TIM5_CH3, USART2_TX, LCD_SEG1, SAI2_EXTCLK and WKUP4/LSCO.
17 PA3 bidirectional TT_la I/O, 3.6 V tolerant (analog switch supplied by VDDA), with ADC12_IN8 and OPAMP1_VOUT, plus TIM2_CH4, TIM5_CH4, USART2_RX, LCD_SEG2 and TIM15_CH2.
18 VSS power_in Ground pin, to be connected to the external ground together with the other VSS pins.
19 VDD power_in Main supply pin, standard operating voltage 1.71 V to 3.6 V.
20 PA4 bidirectional TT_a I/O, 3.6 V tolerant (analog switch supplied by VDDA), with ADC12_IN9 and DAC1_OUT1 analog functions, plus SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B and LPTIM2_OUT.
21 PA5 bidirectional TT_a I/O, 3.6 V tolerant (analog switch supplied by VDDA), with ADC12_IN10 and DAC1_OUT2 analog functions, plus TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK and LPTIM2_ETR.
22 PA6 bidirectional FT_la I/O (analog switch supplied by VDDA) with ADC12_IN11 and OPAMP2_VINP inputs, plus TIM1_BKIN, TIM3_CH1, SPI1_MISO, USART3_CTS, QUADSPI_BK1_IO3 and TIM16_CH1.
23 PA7 bidirectional FT_la I/O (analog switch supplied by VDDA) with ADC12_IN12 and OPAMP2_VINM inputs, plus TIM1_CH1N, TIM3_CH2, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4 and TIM17_CH1.
24 PC4 bidirectional FT_la I/O (analog switch supplied by VDDA) with ADC12_IN13 and COMP1_INM inputs, plus USART3_TX and LCD_SEG22.
25 PC5 bidirectional FT_la I/O (analog switch supplied by VDDA) with ADC12_IN14, COMP1_INP and WKUP5 inputs, plus USART3_RX and LCD_SEG23.
26 PB0 bidirectional TT_la I/O, 3.6 V tolerant (analog switch supplied by VDDA) with ADC12_IN15 and OPAMP2_VOUT, plus TIM1_CH2N, TIM3_CH3, USART3_CK, QUADSPI_BK1_IO1 and COMP1_OUT.
27 PB1 bidirectional FT_la I/O (analog switch supplied by VDDA) with ADC12_IN16 and COMP1_INM inputs, plus TIM1_CH3N, TIM3_CH4, DFSDM1_DATIN0, USART3_RTS_DE and QUADSPI_BK1_IO0.
28 PB2 bidirectional FT_a I/O (analog switch supplied by VDDA) with COMP1_INP input, plus RTC_OUT, LPTIM1_OUT, I2C3_SMBA and DFSDM1_CKIN0.
29 PB10 bidirectional FT_fl I/O (Fm+ capable, LCD function supplied by VLCD), with TIM2_CH3, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, QUADSPI_CLK, LCD_SEG10 and COMP1_OUT.
30 PB11 bidirectional FT_fl I/O (Fm+ capable, LCD function supplied by VLCD), with TIM2_CH4, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_NCS, LCD_SEG11 and COMP2_OUT.
31 VSS power_in Ground pin, to be connected to the external ground together with the other VSS pins.
32 VDD power_in Main supply pin, standard operating voltage 1.71 V to 3.6 V.
33 PB12 bidirectional FT_l I/O (LCD function supplied by VLCD), with TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, LCD_SEG12 and TIM15_BKIN.
34 PB13 bidirectional FT_fl I/O (Fm+ capable, LCD function supplied by VLCD), with TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, LCD_SEG13 and TIM15_CH1N.
35 PB14 bidirectional FT_fl I/O (Fm+ capable, LCD function supplied by VLCD), with TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14 and TIM15_CH1.
36 PB15 bidirectional FT_l I/O (LCD function supplied by VLCD), with RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, LCD_SEG15 and TIM15_CH2.
37 PC6 bidirectional FT_l I/O (LCD function supplied by VLCD), with TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, LCD_SEG24, SDMMC1_D6 and SAI2_MCLK_A.
38 PC7 bidirectional FT_l I/O (LCD function supplied by VLCD), with TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, LCD_SEG25, SDMMC1_D7 and SAI2_MCLK_B.
39 PC8 bidirectional FT_l I/O (LCD function supplied by VLCD), with TIM3_CH3, TIM8_CH3, TSC_G4_IO3, LCD_SEG26, SDMMC1_D0 and EVENTOUT.
40 PC9 bidirectional FT_l I/O (LCD function supplied by VLCD), with TIM8_BKIN2, TIM3_CH4, TIM8_CH4, TSC_G4_IO4, OTG_FS_NOE, LCD_SEG27, SDMMC1_D1 and SAI2_EXTCLK.
41 PA8 bidirectional FT_l I/O (LCD function supplied by VLCD), with MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF, LCD_COM0 and LPTIM2_OUT.
42 PA9 bidirectional FT_lu I/O (LCD function supplied by VLCD, USB function supplied by VDDUSB), with TIM1_CH2, USART1_TX, LCD_COM1, TIM15_BKIN and OTG_FS_VBUS.
43 PA10 bidirectional FT_lu I/O (LCD function supplied by VLCD, USB function supplied by VDDUSB), with TIM1_CH3, USART1_RX, OTG_FS_ID, LCD_COM2 and TIM17_BKIN.
44 PA11 bidirectional FT_u I/O (USB function supplied by VDDUSB), with TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX, OTG_FS_DM and TIM1_BKIN2_COMP1.
45 PA12 bidirectional FT_u I/O (USB function supplied by VDDUSB), with TIM1_ETR, USART1_RTS_DE, CAN1_TX and OTG_FS_DP.
46 PA13 (JTMS-SWDIO) bidirectional FT I/O that after reset is the JTMS-SWDIO debug function with internal pull-up enabled, also available as IR_OUT, OTG_FS_NOE and EVENTOUT.
47 VSS power_in Ground pin, to be connected to the external ground together with the other VSS pins.
48 VDDUSB power_in USB supply pin, 3.0 V to 3.6 V when USB is used (0 V to 3.6 V if USB is not used).
49 PA14 (JTCK-SWCLK) bidirectional FT I/O that after reset is the JTCK-SWCLK debug function with internal pull-down enabled, also available as EVENTOUT.
50 PA15 (JTDI) bidirectional FT_l I/O (LCD function supplied by VLCD) that after reset is the JTDI debug function with internal pull-up enabled, also available as TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, UART4_RTS_DE and LCD_SEG17.
51 PC10 bidirectional FT_l I/O (LCD function supplied by VLCD), with SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, LCD_COM4/LCD_SEG28/LCD_SEG40, SDMMC1_D2 and SAI2_SCK_B.
52 PC11 bidirectional FT_l I/O (LCD function supplied by VLCD), with SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, LCD_COM5/LCD_SEG29/LCD_SEG41, SDMMC1_D3 and SAI2_MCLK_B.
53 PC12 bidirectional FT_l I/O (LCD function supplied by VLCD), with SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, LCD_COM6/LCD_SEG30/LCD_SEG42, SDMMC1_CK and SAI2_SD_B.
54 PD2 bidirectional FT_l I/O (LCD function supplied by VLCD), with TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, LCD_COM7/LCD_SEG31/LCD_SEG43 and SDMMC1_CMD.
55 PB3 (JTDO-TRACESWO) bidirectional FT_la I/O (analog switch supplied by VDDA) that after reset is the JTDO-TRACESWO debug function, also available as TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, LCD_SEG7 and SAI1_SCK_B.
56 PB4 (NJTRST) bidirectional FT_la I/O (analog switch supplied by VDDA) that after reset is the NJTRST debug function with internal pull-up enabled, also available as TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, TSC_G2_IO1, LCD_SEG8 and COMP2_INP.
57 PB5 bidirectional FT_la I/O (analog switch supplied by VDDA) with LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, LCD_SEG9, COMP2_OUT and SAI1_SD_B.
58 PB6 bidirectional FT_fa I/O (Fm+ capable, analog switch supplied by VDDA) with COMP2_INP input, plus LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, DFSDM1_DATIN5, USART1_TX and SAI1_FS_B.
59 PB7 bidirectional FT_fla I/O (Fm+ capable, LCD function supplied by VLCD, analog switch supplied by VDDA) with COMP2_INM and PVD_IN inputs, plus LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, USART1_RX, LCD_SEG21 and FMC_NL.
60 BOOT0 input Dedicated BOOT0 boot-mode selection pin, specified input voltage 0 V to 9 V.
61 PB8 bidirectional FT_fl I/O (Fm+ capable, LCD function supplied by VLCD), with TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A and TIM16_CH1.
62 PB9 bidirectional FT_fl I/O (Fm+ capable, LCD function supplied by VLCD), with IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, LCD_COM3, SDMMC1_D5, SAI1_FS_A and TIM17_CH1.
63 VSS power_in Ground pin, to be connected to the external ground together with the other VSS pins.
64 VDD power_in Main supply pin, standard operating voltage 1.71 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32L486RGT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32l486rgt6-etched.step / stm32l486rgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l486rgt6.step / stm32l486rgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (259 pp, sha256 2406e2ca9710b988, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF