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STM32L476RGT3

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32L476RGT3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32L476RGT3 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply for the RTC and 32x32-bit backup registers, with a backup operating voltage of 1.55 V to 3.6 V.
2 PC13 bidirectional 5 V-tolerant (FT) GPIO also used for RTC tamper/WKUP2; it is supplied through the power switch, which limits it to 3 mA, so output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source.
3 PC14-OSC32_IN (PC14) bidirectional 5 V-tolerant (FT) GPIO that doubles as the 32 kHz LSE oscillator input OSC32_IN, with the same 3 mA power-switch limit as PC13.
4 PC15-OSC32_OUT (PC15) bidirectional 5 V-tolerant (FT) GPIO that doubles as the 32 kHz LSE oscillator output OSC32_OUT, with the same 3 mA power-switch limit as PC13.
5 PH0-OSC_IN (PH0) bidirectional 5 V-tolerant (FT) GPIO that doubles as the HSE oscillator input OSC_IN.
6 PH1-OSC_OUT (PH1) bidirectional 5 V-tolerant (FT) GPIO that doubles as the HSE oscillator output OSC_OUT.
7 NRST bidirectional Bidirectional active-low reset pin with an embedded weak pull-up resistor.
8 PC0 bidirectional 5 V-tolerant I/O (FT_fla: Fm+ capable, LCD function supplied by VLCD, analog switch supplied by VDDA) with ADC123_IN1 input and LPUART1_RX, I2C3_SCL and LPTIM1_IN1 alternate functions.
9 PC1 bidirectional 5 V-tolerant I/O (FT_fla: Fm+ capable, LCD function supplied by VLCD, analog switch supplied by VDDA) with ADC123_IN2 input and LPUART1_TX, I2C3_SDA and LPTIM1_OUT alternate functions.
10 PC2 bidirectional 5 V-tolerant I/O (FT_la: LCD function supplied by VLCD, analog switch supplied by VDDA) with ADC123_IN3 input and SPI2_MISO, LPTIM1_IN2 and LCD_SEG20 alternate functions.
11 PC3 bidirectional 5 V-tolerant I/O (FT_a: analog switch supplied by VDDA) with ADC123_IN4 input and SPI2_MOSI, LPTIM1_ETR and LCD_VLCD alternate functions.
12 VSSA/VREF- power_in Analog ground pin that also serves as the negative ADC reference VREF-, which equals VSSA.
13 VDDA/VREF+ power_in Analog supply pin, 1.62 V to 3.6 V when the ADC or COMP is used, that also serves as the positive ADC reference VREF+.
14 PA0 bidirectional 5 V-tolerant I/O (FT_a) with ADC12_IN5, OPAMP1_VINP and RTC_TAMP2/WKUP1 functions, plus TIM2_CH1, USART2_CTS and UART4_TX alternate functions.
15 PA1 bidirectional 5 V-tolerant I/O (FT_la) with ADC12_IN6 and OPAMP1_VINM functions, plus TIM2_CH2, USART2_RTS_DE and UART4_RX alternate functions.
16 PA2 bidirectional 5 V-tolerant I/O (FT_la) with ADC12_IN7 and WKUP4/LSCO functions, plus TIM2_CH3, USART2_TX and SAI2_EXTCLK alternate functions.
17 PA3 bidirectional 3.6 V-tolerant I/O (TT_la) with ADC12_IN8 and OPAMP1_VOUT functions, plus TIM2_CH4, USART2_RX and TIM15_CH2 alternate functions.
18 VSS power_in Ground pin that must be connected to the external ground within the permitted range.
19 VDD power_in Main digital and I/O supply pin, 1.71 V to 3.6 V.
20 PA4 bidirectional 3.6 V-tolerant I/O (TT_a) with ADC12_IN9 and DAC1_OUT1 functions, plus SPI1_NSS, SPI3_NSS, USART2_CK and LPTIM2_OUT alternate functions.
21 PA5 bidirectional 3.6 V-tolerant I/O (TT_a) with ADC12_IN10 and DAC1_OUT2 functions, plus TIM2_CH1, TIM2_ETR, SPI1_SCK and LPTIM2_ETR alternate functions.
22 PA6 bidirectional 5 V-tolerant I/O (FT_la) with ADC12_IN11 and OPAMP2_VINP functions, plus TIM1_BKIN, TIM3_CH1, SPI1_MISO, USART3_CTS and QUADSPI_BK1_IO3 alternate functions.
23 PA7 bidirectional 5 V-tolerant I/O (FT_la) with ADC12_IN12 and OPAMP2_VINM functions, plus TIM1_CH1N, TIM3_CH2, SPI1_MOSI and QUADSPI_BK1_IO2 alternate functions.
24 PC4 bidirectional 5 V-tolerant I/O (FT_la) with ADC12_IN13 and COMP1_INM functions, plus USART3_TX and LCD_SEG22 alternate functions.
25 PC5 bidirectional 5 V-tolerant I/O (FT_la) with ADC12_IN14, COMP1_INP and WKUP5 functions, plus USART3_RX and LCD_SEG23 alternate functions.
26 PB0 bidirectional 3.6 V-tolerant I/O (TT_la) with ADC12_IN15 and OPAMP2_VOUT functions, plus TIM1_CH2N, TIM3_CH3, USART3_CK and QUADSPI_BK1_IO1 alternate functions.
27 PB1 bidirectional 5 V-tolerant I/O (FT_la) with ADC12_IN16 and COMP1_INM functions, plus TIM1_CH3N, TIM3_CH4, DFSDM1_DATIN0, USART3_RTS_DE and QUADSPI_BK1_IO0 alternate functions.
28 PB2 bidirectional 5 V-tolerant I/O (FT_a) with COMP1_INP function, plus RTC_OUT, LPTIM1_OUT, I2C3_SMBA and DFSDM1_CKIN0 alternate functions.
29 PB10 bidirectional 5 V-tolerant I/O (FT_fl: Fm+ capable, LCD function supplied by VLCD) with TIM2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX and QUADSPI_CLK alternate functions.
30 PB11 bidirectional 5 V-tolerant I/O (FT_fl: Fm+ capable, LCD function supplied by VLCD) with TIM2_CH4, I2C2_SDA, USART3_RX, LPUART1_TX and QUADSPI_NCS alternate functions.
31 VSS power_in Ground pin that must be connected to the external ground within the permitted range.
32 VDD power_in Main digital and I/O supply pin, 1.71 V to 3.6 V.
33 PB12 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with TIM1_BKIN, I2C2_SMBA, SPI2_NSS, USART3_CK and LPUART1_RTS_DE alternate functions.
34 PB13 bidirectional 5 V-tolerant I/O (FT_fl: Fm+ capable, LCD function supplied by VLCD) with TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS and LPUART1_CTS alternate functions.
35 PB14 bidirectional 5 V-tolerant I/O (FT_fl: Fm+ capable, LCD function supplied by VLCD) with TIM1_CH2N, I2C2_SDA, SPI2_MISO, USART3_RTS_DE and TSC_G1_IO3 alternate functions.
36 PB15 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with RTC_REFIN, TIM1_CH3N, SPI2_MOSI and DFSDM1_CKIN2 alternate functions.
37 PC6 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, SDMMC1_D6 and SAI2_MCLK_A alternate functions.
38 PC7 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, SDMMC1_D7 and SAI2_MCLK_B alternate functions.
39 PC8 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with TIM3_CH3, TIM8_CH3, TSC_G4_IO3 and SDMMC1_D0 alternate functions.
40 PC9 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with TIM3_CH4, TIM8_CH4, OTG_FS_NOE, SDMMC1_D1 and SAI2_EXTCLK alternate functions.
41 PA8 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF and LPTIM2_OUT alternate functions.
42 PA9 bidirectional 5 V-tolerant I/O (FT_lu: LCD supplied by VLCD, USB function supplied by VDDUSB) with TIM1_CH2, USART1_TX, TIM15_BKIN and OTG_FS_VBUS functions.
43 PA10 bidirectional 5 V-tolerant I/O (FT_lu: LCD supplied by VLCD, USB function supplied by VDDUSB) with TIM1_CH3, USART1_RX, OTG_FS_ID and TIM17_BKIN alternate functions.
44 PA11 bidirectional 5 V-tolerant I/O (FT_u: USB function supplied by VDDUSB) with TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX and OTG_FS_DM alternate functions.
45 PA12 bidirectional 5 V-tolerant I/O (FT_u: USB function supplied by VDDUSB) with TIM1_ETR, USART1_RTS_DE, CAN1_TX and OTG_FS_DP alternate functions.
46 PA13 (JTMS-SWDIO) bidirectional 5 V-tolerant I/O (FT) that after reset is the JTMS-SWDIO debug function with an internal pull-up enabled, and also provides IR_OUT and OTG_FS_NOE alternate functions.
47 VSS power_in Ground pin that must be connected to the external ground within the permitted range.
48 VDDUSB power_in USB supply pin, 3.0 V to 3.6 V when the USB is used.
49 PA14 (JTCK-SWCLK) bidirectional 5 V-tolerant I/O (FT) that after reset is the JTCK-SWCLK debug function with an internal pull-down enabled.
50 PA15 (JTDI) bidirectional 5 V-tolerant I/O (FT_l) that after reset is the JTDI debug function with an internal pull-up enabled, and also provides TIM2_CH1, SPI1_NSS, SPI3_NSS and LCD_SEG17 alternate functions.
51 PC10 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, SDMMC1_D2 and SAI2_SCK_B alternate functions.
52 PC11 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, SDMMC1_D3 and SAI2_MCLK_B alternate functions.
53 PC12 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, SDMMC1_CK and SAI2_SD_B alternate functions.
54 PD2 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD) with TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC and SDMMC1_CMD alternate functions.
55 PB3 (JTDO-TRACESWO) bidirectional 5 V-tolerant I/O (FT_la) that after reset is the JTDO-TRACESWO debug function, with TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE and SAI1_SCK_B alternate functions.
56 PB4 (NJTRST) bidirectional 5 V-tolerant I/O (FT_la) that after reset is the NJTRST debug function with an internal pull-up enabled, with TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS and TIM17_BKIN alternate functions.
57 PB5 bidirectional 5 V-tolerant I/O (FT_la) with LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK and TIM16_BKIN alternate functions.
58 PB6 bidirectional 5 V-tolerant I/O (FT_fa: Fm+ capable, analog switch supplied by VDDA) with COMP2_INP function, plus LPTIM1_ETR, TIM4_CH1, I2C1_SCL, USART1_TX and TIM16_CH1N alternate functions.
59 PB7 bidirectional 5 V-tolerant I/O (FT_fla: Fm+ capable, LCD supplied by VLCD, analog switch supplied by VDDA) with COMP2_INM and PVD_IN functions, plus LPTIM1_IN2, TIM4_CH2, I2C1_SDA, USART1_RX and FMC_NL alternate functions.
60 BOOT0 input Dedicated BOOT0 boot-mode input whose voltage must stay between 0 V and 9 V.
61 PB8 bidirectional 5 V-tolerant I/O (FT_fl: Fm+ capable, LCD function supplied by VLCD) with TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, SDMMC1_D4 and TIM16_CH1 alternate functions.
62 PB9 bidirectional 5 V-tolerant I/O (FT_fl: Fm+ capable, LCD function supplied by VLCD) with IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, CAN1_TX, SDMMC1_D5 and TIM17_CH1 alternate functions.
63 VSS power_in Ground pin that must be connected to the external ground within the permitted range.
64 VDD power_in Main digital and I/O supply pin, 1.71 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32L476RGT3
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32l476rgt3-etched.step / stm32l476rgt3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l476rgt3.step / stm32l476rgt3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (270 pp, sha256 241f8f908b7f839d, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF