# STM32L471VET6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32L471VET6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V-tolerant GPIO with TRACECK, TIM3_ETR, TSC_G7_IO1, FMC_A23, SAI1_MCLK_A alternate functions; set as analog input after reset. |
| 2 | PE3 | bidirectional | 5 V-tolerant GPIO with TRACED0, TIM3_CH1, TSC_G7_IO2, FMC_A19, SAI1_SD_B alternate functions; set as analog input after reset. |
| 3 | PE4 | bidirectional | 5 V-tolerant GPIO with TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, FMC_A20, SAI1_FS_A alternate functions; set as analog input after reset. |
| 4 | PE5 | bidirectional | 5 V-tolerant GPIO with TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, FMC_A21, SAI1_SCK_A alternate functions; set as analog input after reset. |
| 5 | PE6 | bidirectional | 5 V-tolerant GPIO with TRACED3, TIM3_CH4, FMC_A22, SAI1_SD_A alternate functions; RTC_TAMP3/WKUP3 additional function; set as analog input after reset. |
| 6 | VBAT | power_in | Backup domain supply, 1.55 V to 3.6 V, powering RTC, LSE oscillator, and 32×32-bit backup registers; decoupled with 100 nF + 1 µF. |
| 7 | PC13 | bidirectional | 5 V-tolerant GPIO supplied through backup power switch (max 3 mA, ≤2 MHz, ≤30 pF); RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2 additional functions. |
| 8 | PC14-OSC32_IN | bidirectional | 5 V-tolerant GPIO or LSE 32 kHz oscillator input (OSC32_IN); supplied through backup power switch, max output 3 mA at ≤2 MHz. |
| 9 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant GPIO or LSE 32 kHz oscillator output (OSC32_OUT); supplied through backup power switch, max output 3 mA at ≤2 MHz. |
| 10 | VSS | power_in | Ground reference for the VDD supply domain; must be connected to external ground. |
| 11 | VDD | power_in | Main digital supply voltage, 1.71 V to 3.6 V; powers core logic and I/Os; decouple with n×100 nF + 4.7 µF per supply pair. |
| 12 | PH0-OSC_IN | bidirectional | 5 V-tolerant GPIO or HSE oscillator input (OSC_IN), 4-48 MHz crystal; EVENTOUT alternate function. |
| 13 | PH1-OSC_OUT | bidirectional | 5 V-tolerant GPIO or HSE oscillator output (OSC_OUT); EVENTOUT alternate function. |
| 14 | NRST | bidirectional | Active-low bidirectional reset pin with internal weak pull-up; minimum valid low pulse is device-dependent; filter capacitor recommended per Figure 25. |
| 15 | PC0 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_fa); LPTIM1_IN1, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX, LPTIM2_IN1 alternate functions; ADC123_IN1 additional function. |
| 16 | PC1 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_fa); LPTIM1_OUT, I2C3_SDA, DFSDM1_CKIN4, LPUART1_TX alternate functions; ADC123_IN2 additional function. |
| 17 | PC2 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT alternate functions; ADC123_IN3 additional function. |
| 18 | PC3 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR alternate functions; ADC123_IN4 additional function. |
| 19 | VSSA | power_in | Analog ground reference for ADC, DAC, OPAMP, COMP; must be connected to VSS. |
| 20 | VREF- | power_in | ADC/DAC negative reference voltage; connected to VSSA; must always be connected per Table 20 footnote. |
| 21 | VREF+ | power_in | ADC positive reference input, 2.0 V to VDDA (when VDDA ≥ 2 V); also serves as VREFBUF_OUT when internal voltage reference buffer is enabled. |
| 22 | VDDA | power_in | Analog supply, 1.62-3.6 V for ADC/COMP, ≥1.8 V for DAC/OPAMP, ≥2.4 V for VREFBUF; decouple with 10 nF + 1 µF. |
| 23 | PA0 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI1_EXTCLK alternate functions; OPAMP1_VINP/ADC12_IN5/RTC_TAMP2/WKUP1 additional. |
| 24 | PA1 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); TIM2_CH2, TIM5_CH2, USART2_RTS_DE, UART4_RX, TIM15_CH1N alternate functions; OPAMP1_VINM/ADC12_IN6 additional functions. |
| 25 | PA2 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); TIM2_CH3, TIM5_CH3, USART2_TX, SAI2_EXTCLK, TIM15_CH1 alternate functions; ADC12_IN7/WKUP4/LSCO additional. |
| 26 | PA3 | bidirectional | 3.6 V-tolerant GPIO with analog switch (TT_a); TIM2_CH4, TIM5_CH4, USART2_RX, TIM15_CH2 alternate functions; OPAMP1_VOUT/ADC12_IN8 additional functions. |
| 27 | VSS | power_in | Ground reference for the VDD supply domain; must be connected to external ground. |
| 28 | VDD | power_in | Main digital supply voltage, 1.71 V to 3.6 V; powers core logic and I/Os. |
| 29 | PA4 | bidirectional | 3.6 V-tolerant GPIO with analog switch (TT_a); SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT alternate functions; ADC12_IN9/DAC1_OUT1 additional; negative injection only (-5/0 mA). |
| 30 | PA5 | bidirectional | 3.6 V-tolerant GPIO with analog switch (TT_a); TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR alternate functions; ADC12_IN10/DAC1_OUT2 additional; negative injection only (-5/0 mA). |
| 31 | PA6 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, USART3_CTS, QUADSPI_BK1_IO3, TIM16_CH1 alternate functions; OPAMP2_VINP/ADC12_IN11 additional. |
| 32 | PA7 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, QUADSPI_BK1_IO2, TIM17_CH1 alternate functions; OPAMP2_VINM/ADC12_IN12 additional. |
| 33 | PC4 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); USART3_TX alternate function; COMP1_INM/ADC12_IN13 additional functions. |
| 34 | PC5 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); USART3_RX alternate function; COMP1_INP/ADC12_IN14/WKUP5 additional functions. |
| 35 | PB0 | bidirectional | 3.6 V-tolerant GPIO with analog switch (TT_a); TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT alternate functions; OPAMP2_VOUT/ADC12_IN15 additional. |
| 36 | PB1 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1 alternate functions; COMP1_INM/ADC12_IN16 additional. |
| 37 | PB2 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0 alternate functions; COMP1_INP additional function. |
| 38 | PE7 | bidirectional | 5 V-tolerant GPIO; TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B alternate functions; set as analog input after reset. |
| 39 | PE8 | bidirectional | 5 V-tolerant GPIO; TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B alternate functions; set as analog input after reset. |
| 40 | PE9 | bidirectional | 5 V-tolerant GPIO; TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B alternate functions; set as analog input after reset. |
| 41 | PE10 | bidirectional | 5 V-tolerant GPIO; TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B alternate functions; set as analog input after reset. |
| 42 | PE11 | bidirectional | 5 V-tolerant GPIO; TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, QUADSPI_NCS, FMC_D8 alternate functions; set as analog input after reset. |
| 43 | PE12 | bidirectional | 5 V-tolerant GPIO; TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9 alternate functions; set as analog input after reset. |
| 44 | PE13 | bidirectional | 5 V-tolerant GPIO; TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10 alternate functions; set as analog input after reset. |
| 45 | PE14 | bidirectional | 5 V-tolerant GPIO; TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11 alternate functions; set as analog input after reset. |
| 46 | PE15 | bidirectional | 5 V-tolerant GPIO; TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12 alternate functions; set as analog input after reset. |
| 47 | PB10 | bidirectional | 5 V-tolerant Fm+-capable GPIO (FT_f); TIM2_CH3, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, QUADSPI_CLK, COMP1_OUT, SAI1_SCK_A alternate functions. |
| 48 | PB11 | bidirectional | 5 V-tolerant Fm+-capable GPIO (FT_f); TIM2_CH4, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_NCS, COMP2_OUT alternate functions. |
| 49 | VSS | power_in | Ground reference for the VDD supply domain; must be connected to external ground. |
| 50 | VDD | power_in | Main digital supply voltage, 1.71 V to 3.6 V; powers core logic and I/Os. |
| 51 | PB12 | bidirectional | 5 V-tolerant GPIO; TIM1_BKIN, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN alternate functions. |
| 52 | PB13 | bidirectional | 5 V-tolerant Fm+-capable GPIO (FT_f); TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N alternate functions. |
| 53 | PB14 | bidirectional | 5 V-tolerant Fm+-capable GPIO (FT_f); TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1 alternate functions. |
| 54 | PB15 | bidirectional | 5 V-tolerant GPIO; RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2 alternate functions. |
| 55 | PD8 | bidirectional | 5 V-tolerant GPIO; USART3_TX, FMC_D13 alternate functions; set as analog input after reset. |
| 56 | PD9 | bidirectional | 5 V-tolerant GPIO; USART3_RX, FMC_D14, SAI2_MCLK_A alternate functions; set as analog input after reset. |
| 57 | PD10 | bidirectional | 5 V-tolerant GPIO; USART3_CK, TSC_G6_IO1, FMC_D15, SAI2_SCK_A alternate functions; set as analog input after reset. |
| 58 | PD11 | bidirectional | 5 V-tolerant GPIO; USART3_CTS, TSC_G6_IO2, FMC_A16, SAI2_SD_A, LPTIM2_ETR alternate functions; set as analog input after reset. |
| 59 | PD12 | bidirectional | 5 V-tolerant GPIO; TIM4_CH1, USART3_RTS_DE, TSC_G6_IO3, FMC_A17, SAI2_FS_A, LPTIM2_IN1 alternate functions; set as analog input after reset. |
| 60 | PD13 | bidirectional | 5 V-tolerant GPIO; TIM4_CH2, TSC_G6_IO4, FMC_A18, LPTIM2_OUT alternate functions; set as analog input after reset. |
| 61 | PD14 | bidirectional | 5 V-tolerant GPIO; TIM4_CH3, FMC_D0 alternate functions; set as analog input after reset. |
| 62 | PD15 | bidirectional | 5 V-tolerant GPIO; TIM4_CH4, FMC_D1 alternate functions; set as analog input after reset. |
| 63 | PC6 | bidirectional | 5 V-tolerant GPIO; TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, SDMMC1_D6, SAI2_MCLK_A alternate functions; set as analog input after reset. |
| 64 | PC7 | bidirectional | 5 V-tolerant GPIO; TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, SDMMC1_D7, SAI2_MCLK_B alternate functions; set as analog input after reset. |
| 65 | PC8 | bidirectional | 5 V-tolerant GPIO; TIM3_CH3, TIM8_CH3, TSC_G4_IO3, SDMMC1_D0 alternate functions; set as analog input after reset. |
| 66 | PC9 | bidirectional | 5 V-tolerant GPIO; TIM8_BKIN2, TIM3_CH4, TIM8_CH4, TSC_G4_IO4, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1 alternate functions; set as analog input after reset. |
| 67 | PA8 | bidirectional | 5 V-tolerant GPIO; MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT alternate functions; set as analog input after reset. |
| 68 | PA9 | bidirectional | 5 V-tolerant GPIO; TIM1_CH2, USART1_TX, TIM15_BKIN alternate functions; set as analog input after reset. |
| 69 | PA10 | bidirectional | 5 V-tolerant GPIO; TIM1_CH3, USART1_RX, TIM17_BKIN alternate functions; set as analog input after reset. |
| 70 | PA11 | bidirectional | 5 V-tolerant GPIO; TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1 alternate functions; set as analog input after reset. |
| 71 | PA12 | bidirectional | 5 V-tolerant GPIO; TIM1_ETR, USART1_RTS_DE, CAN1_TX alternate functions; set as analog input after reset. |
| 72 | PA13 | bidirectional | 5 V-tolerant GPIO; JTMS-SWDIO/IR_OUT alternate functions; configured as JTMS-SWDIO with internal pull-up active after reset. |
| 73 | VDD | power_in | Main digital supply voltage, 1.71 V to 3.6 V; powers core logic and I/Os. |
| 74 | VSS | power_in | Ground reference for the VDD supply domain; must be connected to external ground. |
| 75 | VDD | power_in | Main digital supply voltage, 1.71 V to 3.6 V; powers core logic and I/Os. |
| 76 | PA14 | bidirectional | 5 V-tolerant GPIO; JTCK-SWCLK alternate function; configured as JTCK-SWCLK with internal pull-down active after reset. |
| 77 | PA15 | bidirectional | 5 V-tolerant GPIO; JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, UART4_RTS_DE, TSC_G3_IO1, SAI2_FS_B alternate functions; internal pull-up active after reset. |
| 78 | PC10 | bidirectional | 5 V-tolerant GPIO; SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, SDMMC1_D2, SAI2_SCK_B alternate functions; set as analog input after reset. |
| 79 | PC11 | bidirectional | 5 V-tolerant GPIO; SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, SDMMC1_D3, SAI2_MCLK_B alternate functions; set as analog input after reset. |
| 80 | PC12 | bidirectional | 5 V-tolerant GPIO; SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, SDMMC1_CK, SAI2_SD_B alternate functions; set as analog input after reset. |
| 81 | PD0 | bidirectional | 5 V-tolerant GPIO; SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2 alternate functions; set as analog input after reset. |
| 82 | PD1 | bidirectional | 5 V-tolerant GPIO; SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3 alternate functions; set as analog input after reset. |
| 83 | PD2 | bidirectional | 5 V-tolerant GPIO; TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, SDMMC1_CMD alternate functions; set as analog input after reset. |
| 84 | PD3 | bidirectional | 5 V-tolerant GPIO; SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, FMC_CLK alternate functions; set as analog input after reset. |
| 85 | PD4 | bidirectional | 5 V-tolerant GPIO; SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, FMC_NOE alternate functions; set as analog input after reset. |
| 86 | PD5 | bidirectional | 5 V-tolerant GPIO; USART2_TX, FMC_NWE alternate functions; set as analog input after reset. |
| 87 | PD6 | bidirectional | 5 V-tolerant GPIO; DFSDM1_DATIN1, USART2_RX, FMC_NWAIT, SAI1_SD_A alternate functions; set as analog input after reset. |
| 88 | PD7 | bidirectional | 5 V-tolerant GPIO; DFSDM1_CKIN1, USART2_CK, FMC_NE1 alternate functions; set as analog input after reset. |
| 89 | PB3 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B alternate functions; COMP2_INM additional; JTDO active after reset. |
| 90 | PB4 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, SAI1_MCLK_B, TIM17_BKIN alternate functions; COMP2_INP additional; NJTRST active with pull-up after reset. |
| 91 | PB5 | bidirectional | 5 V-tolerant GPIO with analog switch (FT_a); LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN alternate functions. |
| 92 | PB6 | bidirectional | 5 V-tolerant Fm+-capable GPIO with analog switch (FT_fa); LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, DFSDM1_DATIN5, USART1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N alternate functions; COMP2_INP additional. |
| 93 | PB7 | bidirectional | 5 V-tolerant Fm+-capable GPIO with analog switch (FT_fa); LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, FMC_NL, TIM17_CH1N alternate functions; COMP2_INM/PVD_IN additional. |
| 94 | BOOT0 | input | Dedicated boot mode selection input (type B); low = boot from Flash, high = system memory/SRAM; accepts up to 9 V on this pin. |
| 95 | PB8 | bidirectional | 5 V-tolerant Fm+-capable GPIO (FT_f); TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1 alternate functions; set as analog input after reset. |
| 96 | PB9 | bidirectional | 5 V-tolerant Fm+-capable GPIO (FT_f); IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, SDMMC1_D5, SAI1_FS_A, TIM17_CH1 alternate functions; set as analog input after reset. |
| 97 | PE0 | bidirectional | 5 V-tolerant GPIO; TIM4_ETR, FMC_NBL0, TIM16_CH1 alternate functions; set as analog input after reset. |
| 98 | PE1 | bidirectional | 5 V-tolerant GPIO; FMC_NBL1, TIM17_CH1 alternate functions; set as analog input after reset. |
| 99 | VSS | power_in | Ground reference for the VDD supply domain; must be connected to external ground. |
| 100 | VDD | power_in | Main digital supply voltage, 1.71 V to 3.6 V; powers core logic and I/Os. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## CAD (KiCad official)

- Symbol: `STM32L471VET6`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `stm32l471vet6-etched.step` / `stm32l471vet6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32l471vet6.step` / `stm32l471vet6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603177275185909760) (229 pp, sha256 `2a91fd04e0793619`, retrieved 2026-09-24, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32l471vet6-datasheet.pdf)