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STM32L471RET6

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by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32l471ret6factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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STM32L471RET6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32L471RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply, 1.55 V to 3.6 V; powers RTC, 32×32-bit backup registers, and LSE oscillator when VDD is removed (300 nA typical in VBAT mode).
2 PC13 bidirectional FT GPIO PC13, supplied through power switch-output limited to 2 MHz maximum speed and 30 pF maximum load; additional functions: RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2.
3 PC14-OSC32_IN bidirectional FT GPIO PC14 / 32 kHz crystal oscillator input (OSC32_IN); power-switch limited to 2 MHz / 30 pF; additional function: OSC32_IN.
4 PC15-OSC32_OUT bidirectional FT GPIO PC15 / 32 kHz crystal oscillator output (OSC32_OUT); power-switch limited to 2 MHz / 30 pF; additional function: OSC32_OUT.
5 PH0-OSC_IN bidirectional FT GPIO PH0 / HSE crystal oscillator input (OSC_IN); alternate: EVENTOUT; additional: OSC_IN.
6 PH1-OSC_OUT bidirectional FT GPIO PH1 / HSE crystal oscillator output (OSC_OUT); alternate: EVENTOUT; additional: OSC_OUT.
7 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor; driving low asserts system reset; RST-type I/O structure.
8 PC0 bidirectional FT_fa GPIO PC0 (5 V-tolerant, analog switch); alternate: LPTIM1_IN1, I2C3_SCL, DFSDM_DATIN4, LPUART1_RX, LPTIM2_IN1; additional: ADC123_IN1.
9 PC1 bidirectional FT_fa GPIO PC1; alternate: LPTIM1_OUT, I2C3_SDA, DFSDM_CKIN4, LPUART1_TX; additional: ADC123_IN2.
10 PC2 bidirectional FT_a GPIO PC2; alternate: LPTIM1_IN2, SPI2_MISO, DFSDM_CKOUT; additional: ADC123_IN3.
11 PC3 bidirectional FT_a GPIO PC3; alternate: LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR; additional: ADC123_IN4.
12 VSSA/VREF- power_in Analog ground and negative ADC voltage reference; VSSA and VREF− are combined into one pin on LQFP64 and must be connected to external ground.
13 VDDA/VREF+ power_in Analog supply and positive ADC reference (VREFBUF_OUT); VDDA and VREF+ combined on LQFP64; 1.62 V minimum when ADC or COMP is used, 3.6 V maximum.
14 PA0 bidirectional FT_a GPIO PA0; alternate: TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI1_EXTCLK, TIM2_ETR; additional: OPAMP1_VINP, ADC12_IN5, RTC_TAMP2/WKUP1.
15 PA1 bidirectional FT_a GPIO PA1; alternate: TIM2_CH2, TIM5_CH2, USART2_RTS_DE, UART4_RX, TIM15_CH1N; additional: OPAMP1_VINM, ADC12_IN6.
16 PA2 bidirectional FT_a GPIO PA2; alternate: TIM2_CH3, TIM5_CH3, USART2_TX, SAI2_EXTCLK, TIM15_CH1; additional: ADC12_IN7, WKUP4/LSCO.
17 PA3 bidirectional TT GPIO PA3 (3.6 V tolerant); alternate: TIM2_CH4, TIM5_CH4, USART2_RX, TIM15_CH2; additional: OPAMP1_VOUT, ADC12_IN8.
18 VSS power_in Digital ground supply.
19 VDD power_in Main digital supply, 1.71 V to 3.6 V.
20 PA4 bidirectional TT_a GPIO PA4; alternate: SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT; additional: ADC12_IN9, DAC1_OUT1.
21 PA5 bidirectional TT_a GPIO PA5; alternate: TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR; additional: ADC12_IN10, DAC1_OUT2.
22 PA6 bidirectional FT_a GPIO PA6; alternate: TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, USART3_CTS, QUADSPI_BK1_IO3, TIM16_CH1; additional: OPAMP2_VINP, ADC12_IN11.
23 PA7 bidirectional FT_a GPIO PA7; alternate: TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, QUADSPI_BK1_IO2, TIM17_CH1; additional: OPAMP2_VINM, ADC12_IN12.
24 PC4 bidirectional FT_a GPIO PC4; alternate: USART3_TX; additional: COMP1_INM, ADC12_IN13.
25 PC5 bidirectional FT_a GPIO PC5; alternate: USART3_RX; additional: COMP1_INP, ADC12_IN14, WKUP5.
26 PB0 bidirectional TT_a GPIO PB0; alternate: TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT; additional: OPAMP2_VOUT, ADC12_IN15.
27 PB1 bidirectional FT_a GPIO PB1; alternate: TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM_DATIN0, USART3_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1; additional: COMP1_INM, ADC12_IN16.
28 PB2 bidirectional FT_a GPIO PB2; alternate: RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM_CKIN0; additional: COMP1_INP.
29 PB10 bidirectional FT_f (Fm+ capable) GPIO PB10; alternate: TIM2_CH3, I2C2_SCL, SPI2_SCK, DFSDM_DATIN7, USART3_TX, LPUART1_RX, QUADSPI_CLK, COMP1_OUT, SAI1_SCK_A.
30 PB11 bidirectional FT_f (Fm+ capable) GPIO PB11; alternate: TIM2_CH4, I2C2_SDA, DFSDM_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_NCS, COMP2_OUT.
31 VSS power_in Digital ground supply.
32 VDD power_in Main digital supply, 1.71 V to 3.6 V.
33 PB12 bidirectional FT GPIO PB12; alternate: TIM1_BKIN, I2C2_SMBA, SPI2_NSS, DFSDM_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN.
34 PB13 bidirectional FT_f (Fm+ capable) GPIO PB13; alternate: TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N.
35 PB14 bidirectional FT_f (Fm+ capable) GPIO PB14; alternate: TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1.
36 PB15 bidirectional FT GPIO PB15; alternate: RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM_CKIN2, TSC_G1_IO4, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2.
37 PC6 bidirectional FT GPIO PC6; alternate: TIM3_CH1, TIM8_CH1, DFSDM_CKIN3, TSC_G4_IO1, SDMMC1_D6, SAI2_MCLK_A.
38 PC7 bidirectional FT GPIO PC7; alternate: TIM3_CH2, TIM8_CH2, DFSDM_DATIN3, TSC_G4_IO2, SDMMC1_D7, SAI2_MCLK_B.
39 PC8 bidirectional FT GPIO PC8; alternate: TIM3_CH3, TIM8_CH3, TSC_G4_IO3, SDMMC1_D0.
40 PC9 bidirectional FT GPIO PC9; alternate: TIM8_BKIN2, TIM3_CH4, TIM8_CH4, TSC_G4_IO4, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1.
41 PA8 bidirectional FT GPIO PA8; alternate: MCO (clock output), TIM1_CH1, USART1_CK, LPTIM2_OUT.
42 PA9 bidirectional FT GPIO PA9; alternate: TIM1_CH2, USART1_TX, TIM15_BKIN.
43 PA10 bidirectional FT GPIO PA10; alternate: TIM1_CH3, USART1_RX, TIM17_BKIN.
44 PA11 bidirectional FT GPIO PA11; alternate: TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1.
45 PA12 bidirectional FT GPIO PA12; alternate: TIM1_ETR, USART1_RTS_DE, CAN1_TX.
46 PA13 bidirectional FT GPIO PA13; configured as JTMS-SWDIO after reset with internal pull-up active; alternate: IR_OUT; must be reconfigured via software to use as general GPIO.
47 VSS power_in Digital ground supply.
48 VDD power_in Main digital supply, 1.71 V to 3.6 V.
49 PA14 bidirectional FT GPIO PA14; configured as JTCK-SWCLK after reset with internal pull-down active; must be reconfigured via software to use as general GPIO.
50 PA15 bidirectional FT GPIO PA15; configured as JTDI after reset with internal pull-up active; alternate: TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, UART4_RTS_DE, TSC_G3_IO1, SAI2_FS_B.
51 PC10 bidirectional FT GPIO PC10; alternate: SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, SDMMC1_D2, SAI2_SCK_B.
52 PC11 bidirectional FT GPIO PC11; alternate: SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, SDMMC1_D3, SAI2_MCLK_B.
53 PC12 bidirectional FT GPIO PC12; alternate: SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, SDMMC1_CK, SAI2_SD_B.
54 PD2 bidirectional FT GPIO PD2; alternate: TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, SDMMC1_CMD.
55 PB3 bidirectional FT_a GPIO PB3; configured as JTDO-TRACESWO after reset; alternate: TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B; additional: COMP2_INM.
56 PB4 bidirectional FT_a GPIO PB4; configured as NJTRST after reset with internal pull-up active; alternate: TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, SAI1_MCLK_B, TIM17_BKIN; additional: COMP2_INP.
57 PB5 bidirectional FT_a GPIO PB5; alternate: LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN.
58 PB6 bidirectional FT_fa GPIO PB6; alternate: LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, DFSDM_DATIN5, USART1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N; additional: COMP2_INP.
59 PB7 bidirectional FT_fa GPIO PB7; alternate: LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, DFSDM_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, FMC_NL, TIM17_CH1N; additional: COMP2_INM, PVD_IN.
60 BOOT0 input Dedicated BOOT0 input pin (not a GPIO); sampled at reset to select boot mode; accepts 0-9 V absolute maximum; high level selects System Memory or SRAM boot depending on nSWBOOT0 option bit.
61 PB8 bidirectional FT_f (Fm+ capable) GPIO PB8; alternate: TIM4_CH3, I2C1_SCL, DFSDM_DATIN6, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1.
62 PB9 bidirectional FT_f (Fm+ capable) GPIO PB9; alternate: IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM_CKIN6, CAN1_TX, SDMMC1_D5, SAI1_FS_A, TIM17_CH1.
63 VSS power_in Digital ground supply.
64 VDD power_in Main digital supply, 1.71 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32L471RET6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32l471ret6-etched.step / stm32l471ret6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l471ret6.step / stm32l471ret6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (218 pp, sha256 be0260f719f799ce, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF