# STM32L452REI3

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · UFBGA-64

STM32L452REI3 from STMicroelectronics, in a UFBGA-64. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O (FT) fed from the backup-domain power switch, which sinks only 3 mA, so as a GPIO output it must not exceed 2 MHz / 30 pF and must not source current such as an LED; it is the OSC32_IN LSE oscillator input. |
| A2 | PC13 | bidirectional | 5 V-tolerant I/O (FT) on the backup-domain power switch (3 mA sink limit), limited to 2 MHz with a 30 pF maximum load and not to be used as a current source; additional functions include RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2. |
| A3 | PB9 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f, up to 1 Mbit/s I2C) with alternate functions IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, SDMMC1_D5, SAI1_FS_A and EVENTOUT. |
| A4 | PB4 (NJTRST) | bidirectional | 5 V-tolerant Fm+-capable I/O with analog switch function supplied by VDDA (FT_fa); after reset it is the NJTRST JTAG function with its internal pull-up active, and it also offers TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS and COMP2_INP. |
| A5 | PB3 (JTDO/TRACESWO) | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); after reset it is configured as the JTDO/TRACESWO debug function, with alternate functions TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE and SAI1_SCK_B. |
| A6 | PA15 (JTDI) | bidirectional | 5 V-tolerant I/O (FT) that after reset is the JTDI debug function with its internal pull-up activated; alternates include TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE and TSC_G3_IO1. |
| A7 | PA14 (JTCK/SWCLK) | bidirectional | 5 V-tolerant I/O (FT) that after reset is the JTCK/SWCLK debug function with its internal pull-down activated; alternates include LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA and SAI1_FS_B. |
| A8 | PA13 (JTMS/SWDIO) | bidirectional | 5 V-tolerant I/O (FT) that after reset is the JTMS/SWDIO debug function with its internal pull-up activated; alternates include IR_OUT, USB_NOE and SAI1_SD_B. |
| B1 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O (FT) on the backup-domain power switch (3 mA sink limit), limited to 2 MHz with a 30 pF maximum load and not to be used as a current source; it is the OSC32_OUT LSE oscillator output. |
| B2 | VBAT | power_in | Backup-domain supply for the RTC and 32x32-bit backup registers, specified 1.55 V to 3.6 V. |
| B3 | PB8 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions I2C1_SCL, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A and TIM16_CH1. |
| B4 | PH3-BOOT0 | bidirectional | 5 V-tolerant I/O (FT) that is the BOOT0 boot-mode selection pin, with EVENTOUT as its alternate function. |
| B5 | PD2 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TRACED2, TIM3_ETR, USART3_RTS_DE, TSC_SYNC, SDMMC1_CMD and EVENTOUT. |
| B6 | PC11 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3 and SDMMC1_D3. |
| B7 | PC10 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2 and SDMMC1_D2. |
| B8 | PA12 | bidirectional | 5 V-tolerant I/O with USB function supplied by VDDUSB (FT_u); alternates include TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX and USB_DP. |
| C1 | PH0-OSC_IN | bidirectional | 5 V-tolerant I/O (FT) whose default function is the OSC_IN input of the external high-speed oscillator (4 to 48 MHz crystal) with EVENTOUT as alternate. |
| C2 | VSS | power_in | Ground pin; all VSS pins must be connected to the ground plane. |
| C3 | PB7 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_fa); alternates include LPTIM1_IN2, I2C1_SDA, I2C4_SDA, USART1_RX, UART4_CTS and TSC_G2_IO4, and it is also the PVD_IN input and COMP2_INM. |
| C4 | PB5 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions LPTIM1_IN1, TIM3_CH2, CAN1_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B and TIM16_BKIN. |
| C5 | PC12 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TRACED3, SPI3_MOSI, USART3_CK, TSC_G3_IO4 and SDMMC1_CK. |
| C6 | PA10 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions TIM1_CH3, I2C1_SDA, USART1_RX, USB_CRS_SYNC and SAI1_SD_A. |
| C7 | PA9 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions TIM1_CH2, I2C1_SCL, DFSDM1_DATIN1, USART1_TX, SAI1_FS_A and TIM15_BKIN. |
| C8 | PA11 | bidirectional | 5 V-tolerant I/O with USB function supplied by VDDUSB (FT_u); alternates include TIM1_CH4, SPI1_MISO, COMP1_OUT, USART1_CTS, CAN1_RX and USB_DM. |
| D1 | PH1-OSC_OUT | bidirectional | 5 V-tolerant I/O (FT) whose default function is the OSC_OUT output of the external high-speed oscillator, with EVENTOUT as alternate. |
| D2 | VDD | power_in | Main standard supply, 1.71 V to 3.6 V. |
| D3 | PB6 | bidirectional | 5 V-tolerant Fm+-capable I/O with analog switch function supplied by VDDA (FT_fa); alternates include LPTIM1_ETR, I2C1_SCL, I2C4_SCL, USART1_TX, CAN1_TX, SAI1_FS_B and TIM16_CH1N, and it is also COMP2_INP. |
| D4 | VSS | power_in | Ground pin; all VSS pins must be connected to the ground plane. |
| D5 | VSS | power_in | Ground pin; all VSS pins must be connected to the ground plane. |
| D6 | VSS | power_in | Ground pin; all VSS pins must be connected to the ground plane. |
| D7 | PA8 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions MCO, TIM1_CH1, DFSDM1_CKIN1, USART1_CK, SAI1_SCK_A and LPTIM2_OUT. |
| D8 | PC9 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TIM3_CH4, TSC_G4_IO4, USB_NOE and SDMMC1_D1. |
| E1 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| E2 | PC1 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_fa); alternates include TRACED0, LPTIM1_OUT, I2C4_SDA, I2C3_SDA, LPUART1_TX, and it is ADC1_IN2. |
| E3 | PC0 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_fa); alternates include LPTIM1_IN1, I2C4_SCL, I2C3_SCL, LPUART1_RX and LPTIM2_IN1, and it is ADC1_IN1. |
| E4 | VDD | power_in | Main standard supply, 1.71 V to 3.6 V. |
| E5 | VDDUSB | power_in | USB supply: 3.0 V to 3.6 V when USB is used; 0 to 3.6 V when USB is not used. |
| E6 | VDD | power_in | Main standard supply, 1.71 V to 3.6 V. |
| E7 | PC7 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TIM3_CH2, DFSDM1_DATIN3, TSC_G4_IO2 and SDMMC1_D7. |
| E8 | PC8 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TIM3_CH3, TSC_G4_IO3 and SDMMC1_D0. |
| F1 | VSSA/VREF- | power_in | Analog ground combined with the negative ADC reference voltage VREF-, which is connected internally to VSSA in this package. |
| F2 | PC2 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include LPTIM1_IN2, SPI2_MISO and DFSDM1_CKOUT, and it is ADC1_IN3. |
| F3 | PA2 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT and TIM15_CH1, and it is COMP2_INM, ADC1_IN7 and WKUP4/LSCO. |
| F4 | PA5 | bidirectional | 3.6 V-tolerant I/O with analog switch function supplied by VDDA (TT_a); alternates include TIM2_CH1, TIM2_ETR, SPI1_SCK, DFSDM1_CKOUT and LPTIM2_ETR, and it is COMP1_INM, COMP2_INM and ADC1_IN10. |
| F5 | PB0 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include TIM1_CH2N, TIM3_CH3, SPI1_NSS, DFSDM1_CKIN0, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT and SAI1_EXTCLK, and it is ADC1_IN15. |
| F6 | PC6 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TIM3_CH1, DFSDM1_CKIN3, TSC_G4_IO1 and SDMMC1_D6. |
| F7 | PB15 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions RTC_REFIN, TIM1_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SAI1_SD_A and TIM15_CH2. |
| F8 | PB14 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions TIM1_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SAI1_MCLK_A and TIM15_CH1. |
| G1 | PC3 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A and LPTIM2_ETR, and it is ADC1_IN4. |
| G2 | PA0 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include TIM2_CH1, USART2_CTS, UART4_TX, COMP1_OUT, SAI1_EXTCLK and TIM2_ETR, and it is OPAMP1_VINP, COMP1_INM, ADC1_IN5 and RTC_TAMP2/WKUP1. |
| G3 | PA3 | bidirectional | 3.6 V-tolerant I/O with analog switch function supplied by VDDA (TT_a); alternates include TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, SAI1_MCLK_A and TIM15_CH2, and it is OPAMP1_VOUT, COMP2_INP and ADC1_IN8. |
| G4 | PA6 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include TIM1_BKIN, TIM3_CH1, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3 and TIM16_CH1, and it is ADC1_IN11. |
| G5 | PB1 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include TIM1_CH3N, TIM3_CH4, DFSDM1_DATIN0, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0 and LPTIM2_IN1, and it is COMP1_INM and ADC1_IN16. |
| G6 | PB2 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include RTC_OUT, LPTIM1_OUT, I2C3_SMBA and DFSDM1_CKIN0, and it is COMP1_INP. |
| G7 | PB10 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, COMP1_OUT and SAI1_SCK_A. |
| G8 | PB13 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN1_TX, SAI1_SCK_A and TIM15_CH1N. |
| H1 | VDDA/VREF+ | power_in | Analog supply (1.62 V minimum when ADC or COMP is used, 3.6 V maximum) combined with the ADC positive reference VREF+, which is connected internally to VDDA in this package. |
| H2 | PA1 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternates include TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX and TIM15_CH1N, and it is OPAMP1_VINM, COMP1_INP and ADC1_IN6. |
| H3 | PA4 | bidirectional | 3.6 V-tolerant I/O with analog switch function supplied by VDDA (TT_a); alternates include SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B and LPTIM2_OUT, and it is COMP1_INM, COMP2_INM, ADC1_IN9 and DAC1_OUT1. |
| H4 | PA7 | bidirectional | 5 V-tolerant Fm+-capable I/O with analog switch function supplied by VDDA (FT_fa); alternates include TIM1_CH1N, TIM3_CH2, I2C3_SCL, SPI1_MOSI, DFSDM1_DATIN0, QUADSPI_BK1_IO2 and COMP2_OUT, and it is ADC1_IN12. |
| H5 | PC4 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternate function USART3_TX, and it is COMP1_INM and ADC1_IN13. |
| H6 | PC5 | bidirectional | 5 V-tolerant I/O with analog switch function supplied by VDDA (FT_a); alternate function USART3_RX, and it is COMP1_INP, ADC1_IN14 and WKUP5. |
| H7 | PB11 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions TIM2_CH4, I2C4_SDA, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS and COMP2_OUT. |
| H8 | PB12 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN1_RX, SAI1_FS_A and TIM15_BKIN. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFBGA-64 |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `STM32L452REI3`
- Footprint: `Package_BGA:UFBGA-64_5x5mm_Layout8x8_P0.5mm`
- 3D model: UFBGA-64 (KiCad packages3D, STEP)
- 3D model files: `stm32l452rei3-etched.step` / `stm32l452rei3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32l452rei3.step` / `stm32l452rei3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588952285866680320) (221 pp, sha256 `0c90cbe36d057ab4`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32l452rei3-datasheet.pdf)