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STM32L451VCI6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFBGA-100. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32L451VCI6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFBGA-100

STM32L451VCI6 from STMicroelectronics, in a UFBGA-100. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 PE3 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACED0, TIM3_CH1, TSC_G7_IO2, SAI1_SD_B, EVENTOUT.
A2 PE1 bidirectional FT (5 V-tolerant) I/O; alternate function EVENTOUT only.
A3 PB8 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions I2C1_SCL, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT.
A4 PH3-BOOT0 bidirectional I/O with no I/O structure listed; function BOOT0 (boot pin) with alternate function EVENTOUT.
A5 PD7 bidirectional FT (5 V-tolerant) I/O; alternate functions DFSDM1_CKIN1, USART2_CK, QUADSPI_BK2_IO3, EVENTOUT.
A6 PD5 bidirectional FT (5 V-tolerant) I/O; alternate functions USART2_TX, QUADSPI_BK2_IO1, EVENTOUT.
A7 PB4 bidirectional FT_fa (5 V-tolerant, analog switch supplied by VDDA) I/O; NJTRST after reset with internal pull-up enabled (note 3); alternate functions TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, TSC_G2_IO1, SAI1_MCLK_B, EVENTOUT; additional COMP2_INP.
A8 PB3 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; JTDO/TRACESWO after reset (note 3); alternate functions TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B, EVENTOUT; additional COMP2_INM.
A9 PA15 bidirectional FT (5 V-tolerant) I/O; JTDI after reset with internal pull-up enabled (note 3); alternate functions TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, TSC_G3_IO1, EVENTOUT.
A10 PA14 bidirectional FT (5 V-tolerant) I/O; JTCK/SWCLK after reset with internal pull-down enabled (note 3); alternate functions LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA, SAI1_FS_B, EVENTOUT.
A11 PA13 bidirectional FT (5 V-tolerant) I/O; JTMS/SWDAT after reset with internal pull-up enabled (note 3); alternate functions IR_OUT, SAI1_SD_B, EVENTOUT.
A12 PA12 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, EVENTOUT.
B1 PE4 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, SAI1_FS_A, EVENTOUT.
B2 PE2 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACECK, TIM3_ETR, TSC_G7_IO1, SAI1_MCLK_A, EVENTOUT.
B3 PB9 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, SDMMC1_D5, SAI1_FS_A, EVENTOUT.
B4 PB7 bidirectional FT_fa (5 V-tolerant, Fm+ capable, analog switch supplied by VDDA) I/O; alternate functions LPTIM1_IN2, I2C1_SDA, I2C4_SDA, USART1_RX, UART4_CTS, TSC_G2_IO4, EVENTOUT; additional COMP2_INM, PVD_IN.
B5 PB6 bidirectional FT_fa (5 V-tolerant, Fm+ capable, analog switch supplied by VDDA) I/O; alternate functions LPTIM1_ETR, I2C1_SCL, I2C4_SCL, USART1_TX, CAN1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N, EVENTOUT; additional COMP2_INP.
B6 PD6 bidirectional FT (5 V-tolerant) I/O; alternate functions DFSDM1_DATIN1, USART2_RX, QUADSPI_BK2_IO2, SAI1_SD_A, EVENTOUT.
B7 PD4 bidirectional FT (5 V-tolerant) I/O; alternate functions SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, QUADSPI_BK2_IO0, EVENTOUT.
B8 PD3 bidirectional FT (5 V-tolerant) I/O; alternate functions SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, QUADSPI_BK2_NCS, EVENTOUT.
B9 PD1 bidirectional FT (5 V-tolerant) I/O; alternate functions SPI2_SCK, CAN1_TX, EVENTOUT.
B10 PC12 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACED3, SPI3_MOSI, USART3_CK, TSC_G3_IO4, SDMMC1_CK, EVENTOUT.
B11 PC10 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, SDMMC1_D2, EVENTOUT.
B12 PA11 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1, EVENTOUT.
C1 PC13 bidirectional FT (5 V-tolerant) I/O supplied through the power switch, which sinks only about 3 mA, so output use is limited to 2 MHz max at 30 pF max load and it must not source current (note 1); additional functions RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2.
C2 PE5 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, SAI1_SCK_A, EVENTOUT.
C3 PE0 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM16_CH1, EVENTOUT.
C4 VDD power_in Standard operating supply voltage pin, 1.71 V to 3.6 V (Table 23).
C5 PB5 bidirectional FT (5 V-tolerant) I/O; alternate functions LPTIM1_IN1, TIM3_CH2, CAN1_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT.
C8 PD2 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACED2, TIM3_ETR, USART3_RTS_DE, TSC_SYNC, SDMMC1_CMD, EVENTOUT.
C9 PD0 bidirectional FT (5 V-tolerant) I/O; alternate functions SPI2_NSS, CAN1_RX, EVENTOUT.
C10 PC11 bidirectional FT (5 V-tolerant) I/O; alternate functions SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, SDMMC1_D3, EVENTOUT.
C11 VDD power_in Standard operating supply voltage pin, 1.71 V to 3.6 V (Table 23).
C12 PA10 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions TIM1_CH3, I2C1_SDA, USART1_RX, SAI1_SD_A, EVENTOUT.
D1 PC14-OSC32_IN bidirectional FT (5 V-tolerant) I/O supplied through the power switch with the same 3 mA sink limit and 2 MHz / 30 pF output limits as PC13 (note 1); also the LSE oscillator input OSC32_IN.
D2 PE6 bidirectional FT (5 V-tolerant) I/O; alternate functions TRACED3, TIM3_CH4, SAI1_SD_A, EVENTOUT; additional functions RTC_TAMP3, WKUP3.
D3 VSS power_in Ground pin; must be connected to the external supply ground within the permitted range (Table 20, note 1).
D10 PA9 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions TIM1_CH2, I2C1_SCL, DFSDM1_DATIN1, USART1_TX, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
D11 PA8 bidirectional FT (5 V-tolerant) I/O; alternate functions MCO, TIM1_CH1, DFSDM1_CKIN1, USART1_CK, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT.
D12 PC9 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM3_CH4, TSC_G4_IO4, SDMMC1_D1, EVENTOUT.
E1 PC15-OSC32_OUT bidirectional FT (5 V-tolerant) I/O supplied through the power switch with the same 3 mA sink limit and 2 MHz / 30 pF output limits as PC13 (note 1); also the LSE oscillator output OSC32_OUT.
E2 VBAT power_in Backup domain supply, 1.55 V to 3.6 V, supplying the RTC and backup registers (Table 23).
E3 VSS power_in Ground pin; must be connected to the external supply ground within the permitted range (Table 20, note 1).
E10 PC8 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM3_CH3, TSC_G4_IO3, SDMMC1_D0, EVENTOUT.
E11 PC7 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM3_CH2, DFSDM1_DATIN3, TSC_G4_IO2, SDMMC1_D7, EVENTOUT.
E12 PC6 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM3_CH1, DFSDM1_CKIN3, TSC_G4_IO1, SDMMC1_D6, EVENTOUT.
F1 PH0-OSC_IN bidirectional FT (5 V-tolerant) I/O; also the HSE oscillator input OSC_IN; alternate function EVENTOUT.
F2 VSS power_in Ground pin; must be connected to the external supply ground within the permitted range (Table 20, note 1).
F11 VSS power_in Ground pin; must be connected to the external supply ground within the permitted range (Table 20, note 1).
F12 VSS power_in Ground pin; must be connected to the external supply ground within the permitted range (Table 20, note 1).
G1 PH1-OSC_OUT bidirectional FT (5 V-tolerant) I/O; also the HSE oscillator output OSC_OUT; alternate function EVENTOUT.
G2 VDD power_in Standard operating supply voltage pin, 1.71 V to 3.6 V (Table 23).
G11 VDD power_in Standard operating supply voltage pin, 1.71 V to 3.6 V (Table 23).
G12 VDD power_in Standard operating supply voltage pin, 1.71 V to 3.6 V (Table 23).
H1 PC0 bidirectional FT_fa (5 V-tolerant, Fm+ capable, analog switch supplied by VDDA) I/O; alternate functions LPTIM1_IN1, I2C4_SCL, I2C3_SCL, LPUART1_RX, LPTIM2_IN1, EVENTOUT; additional ADC1_IN1.
H2 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor (Table 15).
H3 VDD power_in Standard operating supply voltage pin, 1.71 V to 3.6 V (Table 23).
H10 PD15 bidirectional FT (5 V-tolerant) I/O; alternate function EVENTOUT only.
H11 PD14 bidirectional FT (5 V-tolerant) I/O; alternate function EVENTOUT only.
H12 PD13 bidirectional FT (5 V-tolerant) I/O; alternate functions I2C4_SDA, TSC_G6_IO4, LPTIM2_OUT, EVENTOUT.
J1 VSSA power_in Analog ground pin for the ADC, DAC, OPAMP, COMP and VREFBUF blocks (Table 20, note 1).
J2 PC1 bidirectional FT_fa (5 V-tolerant, Fm+ capable, analog switch supplied by VDDA) I/O; alternate functions TRACED0, LPTIM1_OUT, I2C4_SDA, I2C3_SDA, LPUART1_TX, EVENTOUT; additional ADC1_IN2.
J3 PC2 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, EVENTOUT; additional ADC1_IN3.
J10 PD12 bidirectional FT (5 V-tolerant) I/O; alternate functions I2C4_SCL, USART3_RTS_DE, TSC_G6_IO3, LPTIM2_IN1, EVENTOUT.
J11 PD11 bidirectional FT (5 V-tolerant) I/O; alternate functions I2C4_SMBA, USART3_CTS, TSC_G6_IO2, LPTIM2_ETR, EVENTOUT.
J12 PD10 bidirectional FT (5 V-tolerant) I/O; alternate functions USART3_CK, TSC_G6_IO1, EVENTOUT.
K1 VREF- power_in Negative ADC reference voltage pin, a separate pin on this package; can be internally connected to VSSA depending on the package (Table 67, note 3).
K2 PC3 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR, EVENTOUT; additional ADC1_IN4.
K3 PA2 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, TIM15_CH1, EVENTOUT; additional COMP2_INM, ADC1_IN7, WKUP4, LSCO.
K4 PA5 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM2_CH1, TIM2_ETR, SPI1_SCK, DFSDM1_CKOUT, LPTIM2_ETR, EVENTOUT; additional COMP1_INM, COMP2_INM, ADC1_IN10.
K5 PC4 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions USART3_TX, EVENTOUT; additional COMP1_INM, ADC1_IN13.
K8 PD9 bidirectional FT (5 V-tolerant) I/O; alternate functions USART3_RX, EVENTOUT.
K9 PD8 bidirectional FT (5 V-tolerant) I/O; alternate functions USART3_TX, EVENTOUT.
K10 PB15 bidirectional FT (5 V-tolerant) I/O; alternate functions RTC_REFIN, TIM1_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SAI1_SD_A, TIM15_CH2, EVENTOUT.
K11 PB14 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions TIM1_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SAI1_MCLK_A, TIM15_CH1, EVENTOUT.
K12 PB13 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN1_TX, SAI1_SCK_A, TIM15_CH1N, EVENTOUT.
L1 VREF+ power_in Positive ADC reference voltage: 2 V to VDDA when VDDA is 2 V or higher, and VDDA when VDDA is below 2 V; can be internally connected to VDDA depending on the package (Table 67, note 3); also VREFBUF_OUT.
L2 PA0 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM2_CH1, USART2_CTS, UART4_TX, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT; additional OPAMP1_VINP, COMP1_INM, ADC1_IN5, RTC_TAMP2, WKUP1.
L3 PA3 bidirectional TT_a (3.6 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, SAI1_MCLK_A, TIM15_CH2, EVENTOUT; additional OPAMP1_VOUT, COMP2_INP, ADC1_IN8.
L4 PA6 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM1_BKIN, TIM3_CH1, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, TIM1_BKIN_COMP2, TIM16_CH1, EVENTOUT; additional ADC1_IN11.
L5 PC5 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions USART3_RX, EVENTOUT; additional COMP1_INP, ADC1_IN14, WKUP5.
L6 PB2 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0, EVENTOUT; additional COMP1_INP.
L7 PE8 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH1N, DFSDM1_CKIN2, SAI1_SCK_B, EVENTOUT.
L8 PE10 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH2N, TSC_G5_IO1, QUADSPI_CLK, SAI1_MCLK_B, EVENTOUT.
L9 PE12 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH3N, SPI1_NSS, TSC_G5_IO3, QUADSPI_BK1_IO0, EVENTOUT.
L10 PB10 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, COMP1_OUT, SAI1_SCK_A, EVENTOUT.
L11 PB11 bidirectional FT_f (5 V-tolerant, Fm+ capable) I/O; alternate functions TIM2_CH4, I2C4_SDA, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, EVENTOUT.
L12 PB12 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN1_RX, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
M1 VDDA power_in Analog supply: 1.62 V to 3.6 V when ADC or COMP is used, 1.8 V minimum when DAC or OPAMP is used, and 2.4 V minimum when VREFBUF is used (Table 23).
M2 PA1 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX, TIM15_CH1N, EVENTOUT; additional OPAMP1_VINM, COMP1_INP, ADC1_IN6.
M3 PA4 bidirectional TT_a (3.6 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT; additional COMP1_INM, COMP2_INM, ADC1_IN9, DAC1_OUT1.
M4 PA7 bidirectional FT_fa (5 V-tolerant, Fm+ capable, analog switch supplied by VDDA) I/O; alternate functions TIM1_CH1N, TIM3_CH2, I2C3_SCL, SPI1_MOSI, DFSDM1_DATIN0, QUADSPI_BK1_IO2, COMP2_OUT, EVENTOUT; additional ADC1_IN12.
M5 PB0 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM1_CH2N, TIM3_CH3, SPI1_NSS, DFSDM1_CKIN0, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT, SAI1_EXTCLK, EVENTOUT; additional ADC1_IN15.
M6 PB1 bidirectional FT_a (5 V-tolerant, analog switch supplied by VDDA) I/O; alternate functions TIM1_CH3N, TIM3_CH4, DFSDM1_DATIN0, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1, EVENTOUT; additional COMP1_INM, ADC1_IN16.
M7 PE7 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_ETR, DFSDM1_DATIN2, SAI1_SD_B, EVENTOUT.
M8 PE9 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH1, DFSDM1_CKOUT, SAI1_FS_B, EVENTOUT.
M9 PE11 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH2, TSC_G5_IO2, QUADSPI_BK1_NCS, EVENTOUT.
M10 PE13 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH3, SPI1_SCK, TSC_G5_IO4, QUADSPI_BK1_IO1, EVENTOUT.
M11 PE14 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, EVENTOUT.
M12 PE15 bidirectional FT (5 V-tolerant) I/O; alternate functions TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, EVENTOUT.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFBGA-100
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32L451VCI6
  • Footprint: Package_BGA:UFBGA-100_7x7mm_Layout12x12_P0.5mm
  • 3D model: UFBGA-100 (KiCad packages3D, STEP)
  • 3D model files: stm32l451vci6-etched.step / stm32l451vci6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l451vci6.step / stm32l451vci6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (207 pp, sha256 aa4890e697f5f52e, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF