component
STM32L451RET6TR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
5 files changed
+260−249
README.md+56−56@@ -9,69 +9,69 @@ STM32L451RET6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin des | Pin | Name | Type | Function | |---|---|---|---| | 1 | VBAT | power_in | Backup power supply for RTC and backup registers, voltage range 1.55 V to 3.6 V. |-| 2 | PC14-OSC32_IN | input | GPIO Port C pin 14, 5 V tolerant I/O, can be configured as 32 kHz crystal oscillator input. |-| 3 | PC15-OSC32_OUT | output | GPIO Port C pin 15, 5 V tolerant I/O, can be configured as 32 kHz crystal oscillator output. |-| 4 | PH0-OSC_IN | input | GPIO Port H pin 0, 5 V tolerant I/O, can be configured as main crystal oscillator input. |-| 5 | PH1-OSC_OUT | output | GPIO Port H pin 1, 5 V tolerant I/O, can be configured as main crystal oscillator output. |-| 6 | NRST | bidirectional | Reset pin with embedded weak pull-up resistor, accepts input or open-drain output during reset sequence. |-| 7 | PC0 | bidirectional | GPIO Port C pin 0, 5 V tolerant I/O with analog switch capability, ADC1_IN1 analog input. |-| 8 | PC1 | bidirectional | GPIO Port C pin 1, 5 V tolerant I/O with analog switch capability, ADC1_IN2 analog input. |-| 9 | PC2 | bidirectional | GPIO Port C pin 2, 5 V tolerant I/O with analog switch capability, ADC1_IN3 analog input. |-| 10 | PC3 | bidirectional | GPIO Port C pin 3, 5 V tolerant I/O with analog switch capability, ADC1_IN4 analog input. |-| 11 | VSSA | power_in | Analog ground for ADC and analog peripherals, must be at same potential as VSS. |-| 12 | VDDA | power_in | Analog supply voltage for ADC, DAC, OPAMP, comparators, range 1.62 V to 3.6 V. |-| 13 | PA0 | bidirectional | GPIO Port A pin 0, 5 V tolerant I/O with analog switch capability, ADC1_IN5 analog input. |-| 14 | PA1 | bidirectional | GPIO Port A pin 1, 5 V tolerant I/O with analog switch capability, ADC1_IN6 analog input. |-| 15 | PA2 | bidirectional | GPIO Port A pin 2, 5 V tolerant I/O with analog switch capability, ADC1_IN7 analog input. |-| 16 | PC13 | bidirectional | GPIO Port C pin 13, 5 V tolerant I/O with 3 mA maximum output current limitation, powered through backup domain switch. |+| 2 | PC13 | bidirectional | GPIO Port C pin 13, 5 V tolerant I/O with 3 mA maximum output current limitation, powered through backup domain switch. |+| 3 | PC14-OSC32_IN (PC14) | bidirectional | |+| 4 | PC15-OSC32_OUT (PC15) | bidirectional | |+| 5 | PH0-OSC_IN (PH0) | bidirectional | |+| 6 | PH1-OSC_OUT (PH1) | bidirectional | |+| 7 | NRST | input | Reset pin with embedded weak pull-up resistor, accepts input or open-drain output during reset sequence. |+| 8 | PC0 | bidirectional | GPIO Port C pin 0, 5 V tolerant I/O with analog switch capability, ADC1_IN1 analog input. |+| 9 | PC1 | bidirectional | GPIO Port C pin 1, 5 V tolerant I/O with analog switch capability, ADC1_IN2 analog input. |+| 10 | PC2 | bidirectional | GPIO Port C pin 2, 5 V tolerant I/O with analog switch capability, ADC1_IN3 analog input. |+| 11 | PC3 | bidirectional | GPIO Port C pin 3, 5 V tolerant I/O with analog switch capability, ADC1_IN4 analog input. |+| 12 | VSSA/VREF- | power_in | |+| 13 | VDDA/VREF+ | power_in | |+| 14 | PA0 | bidirectional | GPIO Port A pin 0, 5 V tolerant I/O with analog switch capability, ADC1_IN5 analog input. |+| 15 | PA1 | bidirectional | GPIO Port A pin 1, 5 V tolerant I/O with analog switch capability, ADC1_IN6 analog input. |+| 16 | PA2 | bidirectional | GPIO Port A pin 2, 5 V tolerant I/O with analog switch capability, ADC1_IN7 analog input. | | 17 | PA3 | bidirectional | GPIO Port A pin 3, 3.6 V tolerant I/O with analog switch capability, ADC1_IN8 analog input. | | 18 | VSS | power_in | Ground connection for digital circuits and standard I/O. | | 19 | VDD | power_in | Main digital supply voltage, range 1.71 V to 3.6 V with decoupling capacitor required. | | 20 | PA4 | bidirectional | GPIO Port A pin 4, 3.6 V tolerant I/O with analog switch capability, ADC1_IN9 and DAC1_OUT1 analog functions. | | 21 | PA5 | bidirectional | GPIO Port A pin 5, 3.6 V tolerant I/O with analog switch capability, ADC1_IN10 analog input. |-| 22 | PC4 | bidirectional | GPIO Port C pin 4, 5 V tolerant I/O with analog switch capability, ADC1_IN13 analog input. |-| 23 | PC5 | bidirectional | GPIO Port C pin 5, 5 V tolerant I/O with analog switch capability, ADC1_IN14 and WKUP5 wake-up source. |-| 24 | PB2 | bidirectional | GPIO Port B pin 2, 5 V tolerant I/O with analog switch capability, COMP1_INP comparator input. |-| 25 | PB11 | bidirectional | GPIO Port B pin 11, 5 V tolerant I/O with Fm+ capability for I2C4 and I2C2 communication interfaces. |-| 26 | PA6 | bidirectional | GPIO Port A pin 6, 5 V tolerant I/O with analog switch capability, ADC1_IN11 analog input. |-| 27 | PA7 | bidirectional | GPIO Port A pin 7, 5 V tolerant I/O with analog switch capability, ADC1_IN12 analog input. |-| 28 | PB0 | bidirectional | GPIO Port B pin 0, 5 V tolerant I/O with analog switch capability, ADC1_IN15 analog input. |-| 29 | PB1 | bidirectional | GPIO Port B pin 1, 5 V tolerant I/O with analog switch capability, ADC1_IN16 analog input. |-| 30 | VSS | power_in | Ground connection for digital circuits and standard I/O. |-| 31 | PB10 | bidirectional | GPIO Port B pin 10, 5 V tolerant I/O with Fm+ capability for I2C4, I2C2, and SPI2 interfaces. |+| 22 | PA6 | bidirectional | GPIO Port A pin 6, 5 V tolerant I/O with analog switch capability, ADC1_IN11 analog input. |+| 23 | PA7 | bidirectional | GPIO Port A pin 7, 5 V tolerant I/O with analog switch capability, ADC1_IN12 analog input. |+| 24 | PC4 | bidirectional | GPIO Port C pin 4, 5 V tolerant I/O with analog switch capability, ADC1_IN13 analog input. |+| 25 | PC5 | bidirectional | GPIO Port C pin 5, 5 V tolerant I/O with analog switch capability, ADC1_IN14 and WKUP5 wake-up source. |+| 26 | PB0 | bidirectional | GPIO Port B pin 0, 5 V tolerant I/O with analog switch capability, ADC1_IN15 analog input. |+| 27 | PB1 | bidirectional | GPIO Port B pin 1, 5 V tolerant I/O with analog switch capability, ADC1_IN16 analog input. |+| 28 | PB2 | bidirectional | GPIO Port B pin 2, 5 V tolerant I/O with analog switch capability, COMP1_INP comparator input. |+| 29 | PB10 | bidirectional | GPIO Port B pin 10, 5 V tolerant I/O with Fm+ capability for I2C4, I2C2, and SPI2 interfaces. |+| 30 | PB11 | bidirectional | GPIO Port B pin 11, 5 V tolerant I/O with Fm+ capability for I2C4 and I2C2 communication interfaces. |+| 31 | VSS | power_in | Ground connection for digital circuits and standard I/O. | | 32 | VDD | power_in | Main digital supply voltage, range 1.71 V to 3.6 V with decoupling capacitor required. |-| 33 | VDD | power_in | Main digital supply voltage, range 1.71 V to 3.6 V with decoupling capacitor required. |-| 34 | PA13 | bidirectional | GPIO Port A pin 13, 5 V tolerant I/O, configured as JTMS/SWDIO for debug interface with internal pull-up. |-| 35 | PA12 | bidirectional | GPIO Port A pin 12, 5 V tolerant I/O with Fm+ capability for CAN1_TX and USART1_RTS alternate functions. |-| 36 | PA11 | bidirectional | GPIO Port A pin 11, 5 V tolerant I/O for CAN1_RX and USART1_CTS alternate functions. |-| 37 | PA10 | bidirectional | GPIO Port A pin 10, 5 V tolerant I/O with Fm+ capability for I2C1_SDA and USART1_RX. |-| 38 | PA9 | bidirectional | GPIO Port A pin 9, 5 V tolerant I/O with Fm+ capability for I2C1_SCL and USART1_TX. |-| 39 | PA8 | bidirectional | GPIO Port A pin 8, 5 V tolerant I/O, can be configured as MCO (microcontroller clock output) pin. |+| 33 | PB12 | bidirectional | GPIO Port B pin 12, 5 V tolerant I/O for TIM1_BKIN, I2C2_SMBA, SPI2_NSS alternate functions. |+| 34 | PB13 | bidirectional | GPIO Port B pin 13, 5 V tolerant I/O with Fm+ capability for I2C2_SCL and CAN1_TX. |+| 35 | PB14 | bidirectional | GPIO Port B pin 14, 5 V tolerant I/O with Fm+ capability for I2C2_SDA and SPI2_MISO. |+| 36 | PB15 | bidirectional | GPIO Port B pin 15, 5 V tolerant I/O for TIM1_CH3N, SPI2_MOSI alternate functions. |+| 37 | PC6 | bidirectional | GPIO Port C pin 6, 5 V tolerant I/O for TIM3_CH1, SDMMC1_D6 alternate functions. |+| 38 | PC7 | bidirectional | GPIO Port C pin 7, 5 V tolerant I/O for TIM3_CH2, SDMMC1_D7 alternate functions. |+| 39 | PC8 | bidirectional | GPIO Port C pin 8, 5 V tolerant I/O for TIM3_CH3, SDMMC1_D0 alternate functions. | | 40 | PC9 | bidirectional | GPIO Port C pin 9, 5 V tolerant I/O for TIM3_CH4, TSC_G4_IO4, SDMMC1_D1 alternate functions. |-| 41 | PC8 | bidirectional | GPIO Port C pin 8, 5 V tolerant I/O for TIM3_CH3, SDMMC1_D0 alternate functions. |-| 42 | PC7 | bidirectional | GPIO Port C pin 7, 5 V tolerant I/O for TIM3_CH2, SDMMC1_D7 alternate functions. |-| 43 | PC6 | bidirectional | GPIO Port C pin 6, 5 V tolerant I/O for TIM3_CH1, SDMMC1_D6 alternate functions. |-| 44 | PB15 | bidirectional | GPIO Port B pin 15, 5 V tolerant I/O for TIM1_CH3N, SPI2_MOSI alternate functions. |-| 45 | PB14 | bidirectional | GPIO Port B pin 14, 5 V tolerant I/O with Fm+ capability for I2C2_SDA and SPI2_MISO. |-| 46 | PB13 | bidirectional | GPIO Port B pin 13, 5 V tolerant I/O with Fm+ capability for I2C2_SCL and CAN1_TX. |-| 47 | PB12 | bidirectional | GPIO Port B pin 12, 5 V tolerant I/O for TIM1_BKIN, I2C2_SMBA, SPI2_NSS alternate functions. |-| 48 | VSS | power_in | Ground connection for digital circuits and standard I/O. |-| 49 | VDD | power_in | Main digital supply voltage, range 1.71 V to 3.6 V with decoupling capacitor required. |-| 50 | VSS | power_in | Ground connection for digital circuits and standard I/O. |-| 51 | PB9 | bidirectional | GPIO Port B pin 9, 5 V tolerant I/O with Fm+ capability for I2C1_SDA, CAN1_TX, SDMMC1_D5. |-| 52 | PB8 | bidirectional | GPIO Port B pin 8, 5 V tolerant I/O with Fm+ capability for I2C1_SCL, CAN1_RX, SDMMC1_D4. |-| 53 | PH3-BOOT0 | input | GPIO Port H pin 3 / Boot option pin, selects boot from Flash (0) or system memory (1) at power-up. |-| 54 | PB7 | bidirectional | GPIO Port B pin 7, 5 V tolerant I/O with Fm+ capability for I2C1_SDA, UART4_CTS, COMP2_INM. |-| 55 | PB6 | bidirectional | GPIO Port B pin 6, 5 V tolerant I/O with Fm+ capability for I2C1_SCL, I2C4_SCL, CAN1_TX. |-| 56 | PB5 | bidirectional | GPIO Port B pin 5, 5 V tolerant I/O for LPTIM1_IN1, CAN1_RX, I2C1_SMBA, COMP2_OUT. |-| 57 | PB4 | bidirectional | GPIO Port B pin 4, 5 V tolerant I/O with analog switch and Fm+ capability, NJTRST pin with internal pull-up. |-| 58 | PB3 | bidirectional | GPIO Port B pin 3, 5 V tolerant I/O with analog switch capability, JTDO/TRACESWO pin with internal pull-up. |-| 59 | PD2 | bidirectional | GPIO Port D pin 2, 5 V tolerant I/O for TRACED2, TIM3_ETR, USART3_RTS_DE, SDMMC1_CMD. |-| 60 | PC12 | bidirectional | GPIO Port C pin 12, 5 V tolerant I/O for TRACED3, SPI3_MOSI, USART3_CK, SDMMC1_CK. |-| 61 | PC11 | bidirectional | GPIO Port C pin 11, 5 V tolerant I/O for SPI3_MISO, USART3_RX, UART4_RX, SDMMC1_D3. |-| 62 | PC10 | bidirectional | GPIO Port C pin 10, 5 V tolerant I/O for TRACED1, SPI3_SCK, USART3_TX, SDMMC1_D2. |-| 63 | PA15 | bidirectional | GPIO Port A pin 15, 5 V tolerant I/O, configured as JTDI for debug interface with internal pull-up. |-| 64 | PA14 | bidirectional | GPIO Port A pin 14, 5 V tolerant I/O, configured as JTCK/SWCLK for debug interface with internal pull-down. |+| 41 | PA8 | bidirectional | GPIO Port A pin 8, 5 V tolerant I/O, can be configured as MCO (microcontroller clock output) pin. |+| 42 | PA9 | bidirectional | GPIO Port A pin 9, 5 V tolerant I/O with Fm+ capability for I2C1_SCL and USART1_TX. |+| 43 | PA10 | bidirectional | GPIO Port A pin 10, 5 V tolerant I/O with Fm+ capability for I2C1_SDA and USART1_RX. |+| 44 | PA11 | bidirectional | GPIO Port A pin 11, 5 V tolerant I/O for CAN1_RX and USART1_CTS alternate functions. |+| 45 | PA12 | bidirectional | GPIO Port A pin 12, 5 V tolerant I/O with Fm+ capability for CAN1_TX and USART1_RTS alternate functions. |+| 46 | PA13 (JTMS/SWDIO) | bidirectional | |+| 47 | VSS | power_in | Ground connection for digital circuits and standard I/O. |+| 48 | VDD | power_in | Main digital supply voltage, range 1.71 V to 3.6 V with decoupling capacitor required. |+| 49 | PA14 (JTCK/SWCLK) | bidirectional | |+| 50 | PA15 (JTDI) | bidirectional | |+| 51 | PC10 | bidirectional | GPIO Port C pin 10, 5 V tolerant I/O for TRACED1, SPI3_SCK, USART3_TX, SDMMC1_D2. |+| 52 | PC11 | bidirectional | GPIO Port C pin 11, 5 V tolerant I/O for SPI3_MISO, USART3_RX, UART4_RX, SDMMC1_D3. |+| 53 | PC12 | bidirectional | GPIO Port C pin 12, 5 V tolerant I/O for TRACED3, SPI3_MOSI, USART3_CK, SDMMC1_CK. |+| 54 | PD2 | bidirectional | GPIO Port D pin 2, 5 V tolerant I/O for TRACED2, TIM3_ETR, USART3_RTS_DE, SDMMC1_CMD. |+| 55 | PB3 (JTDO/TRACESWO) | bidirectional | |+| 56 | PB4 (NJTRST) | bidirectional | |+| 57 | PB5 | bidirectional | GPIO Port B pin 5, 5 V tolerant I/O for LPTIM1_IN1, CAN1_RX, I2C1_SMBA, COMP2_OUT. |+| 58 | PB6 | bidirectional | GPIO Port B pin 6, 5 V tolerant I/O with Fm+ capability for I2C1_SCL, I2C4_SCL, CAN1_TX. |+| 59 | PB7 | bidirectional | GPIO Port B pin 7, 5 V tolerant I/O with Fm+ capability for I2C1_SDA, UART4_CTS, COMP2_INM. |+| 60 | PH3-BOOT0 (BOOT0) | bidirectional | |+| 61 | PB8 | bidirectional | GPIO Port B pin 8, 5 V tolerant I/O with Fm+ capability for I2C1_SCL, CAN1_RX, SDMMC1_D4. |+| 62 | PB9 | bidirectional | GPIO Port B pin 9, 5 V tolerant I/O with Fm+ capability for I2C1_SDA, CAN1_TX, SDMMC1_D5. |+| 63 | VSS | power_in | Ground connection for digital circuits and standard I/O. |+| 64 | VDD | power_in | Main digital supply voltage, range 1.71 V to 3.6 V with decoupling capacitor required. | ## Key specifications
package.json+2−2@@ -1,6 +1,6 @@ { "slug": "stm32l451ret6tr",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.", "tags": [@@ -469,4 +469,4 @@ "footprint": "viewers/footprint.html" } }-}+}
page.json+4−4@@ -4,7 +4,7 @@ "slug": "stm32l451ret6tr", "title": "STM32L451RET6TR", "brief": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -496,7 +496,7 @@ "viewers/symbol.html", "viewers/footprint.html" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "org": "adom" }
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prefix="U">- <description></description>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data</description> <gates> <gate name="G$1" symbol="STM32L451RET6TR" x="0" y="0"/> </gates>@@ -226,71 +227,81 @@ <device name="" package="LQFP-64_10x10mm_P0.5mm"> <connects> <connect gate="G$1" pin="VBAT" pad="1"/>- <connect gate="G$1" pin="PC14-OSC32_IN" pad="2"/>- <connect gate="G$1" pin="PC15-OSC32_OUT" pad="3"/>- <connect gate="G$1" pin="PH0-OSC_IN" pad="4"/>- <connect gate="G$1" pin="PH1-OSC_OUT" pad="5"/>- <connect gate="G$1" pin="NRST" pad="6"/>- <connect gate="G$1" pin="PC0" pad="7"/>- <connect gate="G$1" pin="PC1" pad="8"/>- <connect gate="G$1" pin="PC2" pad="9"/>- <connect gate="G$1" pin="PC3" pad="10"/>- <connect gate="G$1" pin="VSSA" pad="11"/>- <connect gate="G$1" pin="VDDA" pad="12"/>- <connect gate="G$1" pin="PA0" pad="13"/>- <connect gate="G$1" pin="PA1" pad="14"/>- <connect gate="G$1" pin="PA2" pad="15"/>- <connect gate="G$1" pin="PC13" pad="16"/>+ <connect gate="G$1" pin="PC13" pad="2"/>+ <connect gate="G$1" pin="PC14-OSC32_IN_PC14" pad="3"/>+ <connect gate="G$1" pin="PC15-OSC32_OUT_PC15" pad="4"/>+ <connect gate="G$1" pin="PH0-OSC_IN_PH0" pad="5"/>+ <connect gate="G$1" pin="PH1-OSC_OUT_PH1" pad="6"/>+ <connect gate="G$1" pin="NRST" pad="7"/>+ <connect gate="G$1" pin="PC0" pad="8"/>+ <connect gate="G$1" pin="PC1" pad="9"/>+ <connect gate="G$1" pin="PC2" pad="10"/>+ <connect gate="G$1" pin="PC3" pad="11"/>+ <connect gate="G$1" pin="VSSA/VREF-" pad="12"/>+ <connect gate="G$1" pin="VDDA/VREF+" pad="13"/>+ <connect gate="G$1" pin="PA0" pad="14"/>+ <connect gate="G$1" pin="PA1" pad="15"/>+ <connect gate="G$1" pin="PA2" pad="16"/> <connect gate="G$1" pin="PA3" pad="17"/> <connect gate="G$1" pin="VSS" pad="18"/> <connect gate="G$1" pin="VDD" pad="19"/> <connect gate="G$1" pin="PA4" pad="20"/> <connect gate="G$1" pin="PA5" pad="21"/>- <connect gate="G$1" pin="PC4" pad="22"/>- <connect gate="G$1" pin="PC5" pad="23"/>- <connect gate="G$1" pin="PB2" pad="24"/>- <connect gate="G$1" pin="PB11" pad="25"/>- <connect gate="G$1" pin="PA6" pad="26"/>- <connect gate="G$1" pin="PA7" pad="27"/>- <connect gate="G$1" pin="PB0" pad="28"/>- <connect gate="G$1" pin="PB1" pad="29"/>- <connect gate="G$1" pin="VSS@2" pad="30"/>- <connect gate="G$1" pin="PB10" pad="31"/>+ <connect gate="G$1" pin="PA6" pad="22"/>+ <connect gate="G$1" pin="PA7" pad="23"/>+ <connect gate="G$1" pin="PC4" pad="24"/>+ <connect gate="G$1" pin="PC5" pad="25"/>+ <connect gate="G$1" pin="PB0" pad="26"/>+ <connect gate="G$1" pin="PB1" pad="27"/>+ <connect gate="G$1" pin="PB2" pad="28"/>+ <connect gate="G$1" pin="PB10" pad="29"/>+ <connect gate="G$1" pin="PB11" pad="30"/>+ <connect gate="G$1" pin="VSS@2" pad="31"/> <connect gate="G$1" pin="VDD@2" pad="32"/>- <connect gate="G$1" pin="PA14" pad="64"/>- <connect gate="G$1" pin="PA15" pad="63"/>- <connect gate="G$1" pin="PC10" pad="62"/>- <connect gate="G$1" pin="PC11" pad="61"/>- <connect gate="G$1" pin="PC12" pad="60"/>- <connect gate="G$1" pin="PD2" pad="59"/>- <connect gate="G$1" pin="PB3" pad="58"/>- <connect gate="G$1" pin="PB4" pad="57"/>- <connect gate="G$1" pin="PB5" pad="56"/>- <connect gate="G$1" pin="PB6" pad="55"/>- <connect gate="G$1" pin="PB7" pad="54"/>- <connect gate="G$1" pin="PH3-BOOT0" pad="53"/>- <connect gate="G$1" pin="PB8" pad="52"/>- <connect gate="G$1" pin="PB9" pad="51"/>- <connect gate="G$1" pin="VSS@3" pad="50"/>- <connect gate="G$1" pin="VDD@3" pad="49"/>- <connect gate="G$1" pin="VSS@4" pad="48"/>- <connect gate="G$1" pin="PB12" pad="47"/>- <connect gate="G$1" pin="PB13" pad="46"/>- <connect gate="G$1" pin="PB14" pad="45"/>- <connect gate="G$1" pin="PB15" pad="44"/>- <connect gate="G$1" pin="PC6" pad="43"/>- <connect gate="G$1" pin="PC7" pad="42"/>- <connect gate="G$1" pin="PC8" pad="41"/>+ <connect gate="G$1" pin="VDD@3" pad="64"/>+ <connect gate="G$1" pin="VSS@3" pad="63"/>+ <connect gate="G$1" pin="PB9" pad="62"/>+ <connect gate="G$1" pin="PB8" pad="61"/>+ <connect gate="G$1" pin="PH3-BOOT0_BOOT0" pad="60"/>+ <connect gate="G$1" pin="PB7" pad="59"/>+ <connect gate="G$1" pin="PB6" pad="58"/>+ <connect gate="G$1" pin="PB5" pad="57"/>+ <connect gate="G$1" pin="PB4_NJTRST" pad="56"/>+ <connect gate="G$1" pin="PB3_JTDO/TRACESWO" pad="55"/>+ <connect gate="G$1" pin="PD2" pad="54"/>+ <connect gate="G$1" pin="PC12" pad="53"/>+ <connect gate="G$1" pin="PC11" pad="52"/>+ <connect gate="G$1" pin="PC10" pad="51"/>+ <connect gate="G$1" pin="PA15_JTDI" pad="50"/>+ <connect gate="G$1" pin="PA14_JTCK/SWCLK" pad="49"/>+ <connect gate="G$1" pin="VDD@4" pad="48"/>+ <connect gate="G$1" pin="VSS@4" pad="47"/>+ <connect gate="G$1" pin="PA13_JTMS/SWDIO" pad="46"/>+ <connect gate="G$1" pin="PA12" pad="45"/>+ <connect gate="G$1" pin="PA11" pad="44"/>+ <connect gate="G$1" pin="PA10" pad="43"/>+ <connect gate="G$1" pin="PA9" pad="42"/>+ <connect gate="G$1" pin="PA8" pad="41"/> <connect gate="G$1" pin="PC9" pad="40"/>- <connect gate="G$1" pin="PA8" pad="39"/>- <connect gate="G$1" pin="PA9" pad="38"/>- <connect gate="G$1" pin="PA10" pad="37"/>- <connect gate="G$1" pin="PA11" pad="36"/>- <connect gate="G$1" pin="PA12" pad="35"/>- <connect gate="G$1" pin="PA13" pad="34"/>- <connect gate="G$1" pin="VDD@4" pad="33"/>+ <connect gate="G$1" pin="PC8" pad="39"/>+ <connect gate="G$1" pin="PC7" pad="38"/>+ <connect gate="G$1" pin="PC6" pad="37"/>+ <connect gate="G$1" pin="PB15" pad="36"/>+ <connect gate="G$1" pin="PB14" pad="35"/>+ <connect gate="G$1" pin="PB13" pad="34"/>+ <connect gate="G$1" pin="PB12" pad="33"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="STM32L451RET6TR" constant="no"/>+ <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590237007227088896" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32l451ret6tr" constant="no"/>+ <attribute name="MOUSER_PN" value="511-STM32L451RET6TR" constant="no"/>+ <attribute name="DIGIKEY_PN" value="497-18835-2-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C5127799" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>