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STM32L451REI6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFBGA-64. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32L451REI6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFBGA-64

STM32L451REI6 from STMicroelectronics, in a UFBGA-64. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 PC14-OSC32_IN bidirectional Bidirectional 5 V-tolerant (FT) GPIO supplied through the backup power switch, which sinks only 3 mA, so output use is limited to 2 MHz at 30 pF maximum and it must not source current such as driving an LED; additional function OSC32_IN.
A2 PC13 bidirectional Bidirectional 5 V-tolerant (FT) GPIO supplied through the backup power switch, limited to 3 mA sink with output speed of 2 MHz maximum at 30 pF and no current-source use; additional functions RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2.
A3 PB9 bidirectional Bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, SDMMC1_D5, SAI1_FS_A, EVENTOUT.
A4 PB4 bidirectional Bidirectional 5 V-tolerant, Fm+ capable, analog-switch I/O (FT_fa) that is configured as the NJTRST JTAG debug function after reset with an internal pull-up enabled; alternate functions include TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, TSC_G2_IO1, SAI1_MCLK_B; additional function COMP2_INP.
A5 PB3 bidirectional Bidirectional 5 V-tolerant, analog-switch I/O (FT_a) that is configured as the JTDO/TRACESWO debug function after reset; alternate functions include TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B; additional function COMP2_INM.
A6 PA15 bidirectional 5 V-tolerant (FT) I/O that is configured as the JTDI debug function after reset with an internal pull-up enabled; alternate functions include TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, TSC_G3_IO1.
A7 PA14 bidirectional 5 V-tolerant (FT) I/O that is configured as the JTCK/SWCLK debug function after reset with an internal pull-down enabled; alternate functions include LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA, SAI1_FS_B.
A8 PA13 bidirectional 5 V-tolerant (FT) I/O that is configured as the JTMS/SWDAT debug function after reset with an internal pull-up enabled; alternate functions include IR_OUT and SAI1_SD_B.
B1 PC15-OSC32_OUT bidirectional Bidirectional 5 V-tolerant (FT) GPIO supplied through the backup power switch, limited to 3 mA sink with 2 MHz maximum output speed at 30 pF and no current-source use; additional function OSC32_OUT.
B2 VBAT power_in Backup-domain supply input for the RTC and 32x32-bit backup registers, with backup operating voltage of 1.55 V to 3.6 V.
B3 PB8 bidirectional Bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions I2C1_SCL, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT.
B4 PH3-BOOT0 bidirectional I/O pin shared with the BOOT0 boot-mode function, with no I/O structure listed in the datasheet and EVENTOUT as its alternate function.
B5 PD2 bidirectional 5 V-tolerant (FT) I/O; alternate functions TRACED2, TIM3_ETR, USART3_RTS_DE, TSC_SYNC, SDMMC1_CMD, EVENTOUT.
B6 PC11 bidirectional 5 V-tolerant (FT) I/O; alternate functions SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, SDMMC1_D3, EVENTOUT.
B7 PC10 bidirectional 5 V-tolerant (FT) I/O; alternate functions TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, SDMMC1_D2, EVENTOUT.
B8 PA12 bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, EVENTOUT.
C1 PH0-OSC_IN bidirectional 5 V-tolerant (FT) I/O; alternate function EVENTOUT and additional function OSC_IN.
C2 VSS power_in Ground (VSS) pin of the digital supply domain.
C3 PB7 bidirectional 5 V-tolerant, analog-switch I/O (FT_fa); alternate functions LPTIM1_IN2, I2C1_SDA, I2C4_SDA, USART1_RX, UART4_CTS, TSC_G2_IO4, EVENTOUT; additional functions COMP2_INM and PVD_IN.
C4 PB5 bidirectional 5 V-tolerant (FT) I/O; alternate functions LPTIM1_IN1, TIM3_CH2, CAN1_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT.
C5 PC12 bidirectional 5 V-tolerant (FT) I/O; alternate functions TRACED3, SPI3_MOSI, USART3_CK, TSC_G3_IO4, SDMMC1_CK, EVENTOUT.
C6 PA10 bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions TIM1_CH3, I2C1_SDA, USART1_RX, SAI1_SD_A, EVENTOUT.
C7 PA9 bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions TIM1_CH2, I2C1_SCL, DFSDM1_DATIN1, USART1_TX, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
C8 PA11 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1, EVENTOUT.
D1 PH1-OSC_OUT bidirectional 5 V-tolerant (FT) I/O; alternate function EVENTOUT and additional function OSC_OUT.
D2 VDD power_in Main digital supply pin, specified for VDD from 1.71 V to 3.6 V.
D3 PB6 bidirectional 5 V-tolerant, analog-switch I/O (FT_fa); alternate functions LPTIM1_ETR, I2C1_SCL, I2C4_SCL, USART1_TX, CAN1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N, EVENTOUT; additional function COMP2_INP.
D4 VSS power_in Ground (VSS) pin of the digital supply domain.
D5 VSS power_in Ground (VSS) pin of the digital supply domain.
D6 VSS power_in Ground (VSS) pin of the digital supply domain.
D7 PA8 bidirectional 5 V-tolerant (FT) I/O; alternate functions MCO, TIM1_CH1, DFSDM1_CKIN1, USART1_CK, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT.
D8 PC9 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_CH4, TSC_G4_IO4, SDMMC1_D1, EVENTOUT.
E1 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
E2 PC1 bidirectional 5 V-tolerant, analog-switch I/O (FT_fa); alternate functions TRACED0, LPTIM1_OUT, I2C4_SDA, I2C3_SDA, LPUART1_TX, EVENTOUT; additional function ADC1_IN2.
E3 PC0 bidirectional 5 V-tolerant, analog-switch I/O (FT_fa); alternate functions LPTIM1_IN1, I2C4_SCL, I2C3_SCL, LPUART1_RX, LPTIM2_IN1, EVENTOUT; additional function ADC1_IN1.
E4 VDD power_in Main digital supply pin, specified for VDD from 1.71 V to 3.6 V.
E5 VDD power_in Main digital supply pin, specified for VDD from 1.71 V to 3.6 V.
E6 VDD power_in Main digital supply pin, specified for VDD from 1.71 V to 3.6 V.
E7 PC7 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_CH2, DFSDM1_DATIN3, TSC_G4_IO2, SDMMC1_D7, EVENTOUT.
E8 PC8 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_CH3, TSC_G4_IO3, SDMMC1_D0, EVENTOUT.
F1 VSSA/VREF- power_in Analog ground pin, which is also the negative reference voltage VREF- on this package.
F2 PC2 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, EVENTOUT; additional function ADC1_IN3.
F3 PA2 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, TIM15_CH1, EVENTOUT; additional functions COMP2_INM, ADC1_IN7, WKUP4, LSCO.
F4 PA5 bidirectional 3.6 V-tolerant (TT_a) I/O; alternate functions TIM2_CH1, TIM2_ETR, SPI1_SCK, DFSDM1_CKOUT, LPTIM2_ETR, EVENTOUT; additional functions COMP1_INM, COMP2_INM, ADC1_IN10.
F5 PB0 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions TIM1_CH2N, TIM3_CH3, SPI1_NSS, DFSDM1_CKIN0, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT, SAI1_EXTCLK, EVENTOUT; additional function ADC1_IN15.
F6 PC6 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM3_CH1, DFSDM1_CKIN3, TSC_G4_IO1, SDMMC1_D6, EVENTOUT.
F7 PB15 bidirectional 5 V-tolerant (FT) I/O; alternate functions RTC_REFIN, TIM1_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SAI1_SD_A, TIM15_CH2, EVENTOUT.
F8 PB14 bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions TIM1_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SAI1_MCLK_A, TIM15_CH1, EVENTOUT.
G1 PC3 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR, EVENTOUT; additional function ADC1_IN4.
G2 PA0 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions TIM2_CH1, USART2_CTS, UART4_TX, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT; additional functions OPAMP1_VINP, COMP1_INM, ADC1_IN5, RTC_TAMP2, WKUP1.
G3 PA3 bidirectional 3.6 V-tolerant, analog-switch I/O (TT_a); alternate functions TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, SAI1_MCLK_A, TIM15_CH2, EVENTOUT; additional functions OPAMP1_VOUT, COMP2_INP, ADC1_IN8.
G4 PA6 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions TIM1_BKIN, TIM3_CH1, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, TIM1_BKIN_COMP2, TIM16_CH1, EVENTOUT; additional function ADC1_IN11.
G5 PB1 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions TIM1_CH3N, TIM3_CH4, DFSDM1_DATIN0, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1, EVENTOUT; additional functions COMP1_INM, ADC1_IN16.
G6 PB2 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0, EVENTOUT; additional function COMP1_INP.
G7 PB10 bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, COMP1_OUT, SAI1_SCK_A, EVENTOUT.
G8 PB13 bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN1_TX, SAI1_SCK_A, TIM15_CH1N, EVENTOUT.
H1 VDDA/VREF+ power_in Analog supply pin, which is also the positive reference voltage VREF+ on this package.
H2 PA1 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX, TIM15_CH1N, EVENTOUT; additional functions OPAMP1_VINM, COMP1_INP, ADC1_IN6.
H3 PA4 bidirectional 3.6 V-tolerant (TT_a) I/O; alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT; additional functions COMP1_INM, COMP2_INM, ADC1_IN9, DAC1_OUT1.
H4 PA7 bidirectional 5 V-tolerant, Fm+ capable, analog-switch I/O (FT_fa); alternate functions TIM1_CH1N, TIM3_CH2, I2C3_SCL, SPI1_MOSI, DFSDM1_DATIN0, QUADSPI_BK1_IO2, COMP2_OUT, EVENTOUT; additional function ADC1_IN12.
H5 PC4 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions USART3_TX and EVENTOUT; additional function COMP1_INM and ADC1_IN13.
H6 PC5 bidirectional 5 V-tolerant, analog-switch I/O (FT_a); alternate functions USART3_RX and EVENTOUT; additional functions COMP1_INP, ADC1_IN14 and WKUP5.
H7 PB11 bidirectional 5 V-tolerant, Fm+ capable (FT_f) I/O; alternate functions TIM2_CH4, I2C4_SDA, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, EVENTOUT.
H8 PB12 bidirectional 5 V-tolerant (FT) I/O; alternate functions TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN1_RX, SAI1_FS_A, TIM15_BKIN, EVENTOUT.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFBGA-64
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32L451REI6
  • Footprint: Package_BGA:UFBGA-64_5x5mm_Layout8x8_P0.5mm
  • 3D model: UFBGA-64 (KiCad packages3D, STEP)
  • 3D model files: stm32l451rei6-etched.step / stm32l451rei6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l451rei6.step / stm32l451rei6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (207 pp, sha256 aa4890e697f5f52e, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF