component
STM32L451CCU6TR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32L451CCU6TR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32L451CCU6TR from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC and 32x32-bit backup registers, with a backup operating voltage of 1.55 V to 3.6 V. |
| 2 | PC13 | bidirectional | 5 V-tolerant GPIO supplied through the power switch, limited to 3 mA sink, output speed no higher than 2 MHz at 30 pF, and not usable as a current source; also RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2. |
| 3 | PC14-OSC32_IN | bidirectional | 5 V-tolerant GPIO with the same power-switch limits as PC13 (3 mA sink, 2 MHz at 30 pF, no current sourcing), and the 32 kHz LSE crystal input OSC32_IN. |
| 4 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant GPIO with the same power-switch limits as PC13 (3 mA sink, 2 MHz at 30 pF, no current sourcing), and the 32 kHz LSE crystal output OSC32_OUT. |
| 5 | PH0-OSC_IN | bidirectional | 5 V-tolerant GPIO that serves as the OSC_IN input of the 4 to 48 MHz crystal oscillator (HSE). |
| 6 | PH1-OSC_OUT | bidirectional | 5 V-tolerant GPIO that serves as the OSC_OUT output of the 4 to 48 MHz crystal oscillator (HSE). |
| 7 | NRST | bidirectional | Bidirectional reset pin with an embedded weak pull-up resistor. |
| 8 | VSSA/VREF- | power_in | Analog ground; on this package the pin is shared with the VREF- negative reference input, which is internally connected to VSSA. |
| 9 | VDDA/VREF+ | power_in | Analog supply, with VDDA at 1.62 V to 3.6 V when the ADC or COMP is used, 1.8 V minimum for DAC or OPAMP, and 2.4 V minimum for VREFBUF; on this package it is shared with the VREF+ reference input. |
| 10 | PA0 | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN5, COMP1_INM, OPAMP1_VINP, TIM2_CH1, USART2_CTS, UART4_TX and WKUP1. |
| 11 | PA1 | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN6, COMP1_INP, OPAMP1_VINM, TIM2_CH2, SPI1_SCK and USART2_RTS_DE. |
| 12 | PA2 | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN7, COMP2_INM, WKUP4, LSCO, TIM2_CH3, USART2_TX, LPUART1_TX and QUADSPI_BK1_NCS. |
| 13 | PA3 | bidirectional | 3.6 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN8, COMP2_INP, OPAMP1_VOUT, TIM2_CH4, USART2_RX, LPUART1_RX and QUADSPI_CLK. |
| 14 | PA4 | bidirectional | 3.6 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN9, DAC1_OUT1, COMP1_INM, COMP2_INM, SPI1_NSS, SPI3_NSS, USART2_CK and SAI1_FS_B. |
| 15 | PA5 | bidirectional | 3.6 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN10, COMP1_INM, COMP2_INM, TIM2_CH1, TIM2_ETR, SPI1_SCK, DFSDM1_CKOUT and LPTIM2_ETR. |
| 16 | PA6 | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN11, TIM1_BKIN, TIM3_CH1, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS and QUADSPI_BK1_IO3. |
| 17 | PA7 | bidirectional | 5 V-tolerant Fm+-capable I/O with an analog switch supplied by VDDA; also ADC1_IN12, TIM1_CH1N, TIM3_CH2, I2C3_SCL, SPI1_MOSI, DFSDM1_DATIN0 and QUADSPI_BK1_IO2. |
| 18 | PB0 | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN15, TIM1_CH2N, TIM3_CH3, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT and SAI1_EXTCLK. |
| 19 | PB1 | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; also ADC1_IN16, COMP1_INM, TIM1_CH3N, TIM3_CH4, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0 and LPTIM2_IN1. |
| 20 | PB2 | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; also COMP1_INP, RTC_OUT, LPTIM1_OUT, I2C3_SMBA and DFSDM1_CKIN0. |
| 21 | PB10 | bidirectional | 5 V-tolerant Fm+-capable I/O; also TIM2_CH3, I2C2_SCL, I2C4_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, COMP1_OUT and SAI1_SCK_A. |
| 22 | PB11 | bidirectional | 5 V-tolerant Fm+-capable I/O; also TIM2_CH4, I2C2_SDA, I2C4_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS and COMP2_OUT. |
| 23 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground, with variation between ground pins limited to 50 mV. |
| 24 | VDD | power_in | Digital supply with a standard operating voltage of 1.71 V to 3.6 V; variation between VDD pins of the same domain is limited to 50 mV. |
| 25 | PB12 | bidirectional | 5 V-tolerant I/O; also TIM1_BKIN, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN1_RX, SAI1_FS_A and TIM15_BKIN. |
| 26 | PB13 | bidirectional | 5 V-tolerant Fm+-capable I/O; also TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN1_TX, SAI1_SCK_A and TIM15_CH1N. |
| 27 | PB14 | bidirectional | 5 V-tolerant Fm+-capable I/O; also TIM1_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SAI1_MCLK_A and TIM15_CH1. |
| 28 | PB15 | bidirectional | 5 V-tolerant I/O; also RTC_REFIN, TIM1_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SAI1_SD_A and TIM15_CH2. |
| 29 | PA8 | bidirectional | 5 V-tolerant I/O; also MCO, TIM1_CH1, DFSDM1_CKIN1, USART1_CK, SAI1_SCK_A and LPTIM2_OUT. |
| 30 | PA9 | bidirectional | 5 V-tolerant Fm+-capable I/O; also TIM1_CH2, I2C1_SCL, DFSDM1_DATIN1, USART1_TX, SAI1_FS_A and TIM15_BKIN. |
| 31 | PA10 | bidirectional | 5 V-tolerant Fm+-capable I/O; also TIM1_CH3, I2C1_SDA, USART1_RX and SAI1_SD_A. |
| 32 | PA11 | bidirectional | 5 V-tolerant I/O; also TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS and CAN1_RX. |
| 33 | PA12 | bidirectional | 5 V-tolerant Fm+-capable I/O; also TIM1_ETR, SPI1_MOSI, USART1_RTS_DE and CAN1_TX. |
| 34 | PA13 (JTMS/SWDIO) | bidirectional | 5 V-tolerant I/O that is configured as the JTMS/SWDIO debug function after reset with its internal pull-up activated; also IR_OUT and SAI1_SD_B. |
| 35 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground, with variation between ground pins limited to 50 mV. |
| 36 | VDD | power_in | Digital supply with a standard operating voltage of 1.71 V to 3.6 V; variation between VDD pins of the same domain is limited to 50 mV. |
| 37 | PA14 (JTCK/SWCLK) | bidirectional | 5 V-tolerant I/O that is configured as the JTCK/SWCLK debug function after reset with its internal pull-down activated; also LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA and SAI1_FS_B. |
| 38 | PA15 (JTDI) | bidirectional | 5 V-tolerant I/O that is configured as the JTDI debug function after reset with its internal pull-up activated; also TIM2_CH1, TIM2_ETR, USART2_RX and SPI1_NSS. |
| 39 | PB3 (JTDO/TRACESWO) | bidirectional | 5 V-tolerant I/O with an analog switch supplied by VDDA; configured as the JTDO/TRACESWO debug function after reset, and also TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE and SAI1_SCK_B. |
| 40 | PB4 (NJTRST) | bidirectional | 5 V-tolerant Fm+-capable I/O with an analog switch supplied by VDDA; configured as NJTRST after reset with its internal pull-up activated, and also TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS and COMP2_INP. |
| 41 | PB5 | bidirectional | 5 V-tolerant I/O; also LPTIM1_IN1, TIM3_CH2, CAN1_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, COMP2_OUT, SAI1_SD_B and TIM16_BKIN. |
| 42 | PB6 | bidirectional | 5 V-tolerant Fm+-capable I/O with an analog switch supplied by VDDA; also LPTIM1_ETR, I2C1_SCL, I2C4_SCL, USART1_TX, CAN1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N and COMP2_INP. |
| 43 | PB7 | bidirectional | 5 V-tolerant Fm+-capable I/O with an analog switch supplied by VDDA; also LPTIM1_IN2, I2C1_SDA, I2C4_SDA, USART1_RX, UART4_CTS, TSC_G2_IO4, COMP2_INM and PVD_IN. |
| 44 | PH3-BOOT0 | bidirectional | Pin with the BOOT0 function; Table 16 gives no I/O structure or tolerance for it, and it is also listed with EVENTOUT. |
| 45 | PB8 | bidirectional | 5 V-tolerant Fm+-capable I/O; also I2C1_SCL, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A and TIM16_CH1. |
| 46 | PB9 | bidirectional | 5 V-tolerant Fm+-capable I/O; also IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, SDMMC1_D5 and SAI1_FS_A. |
| 47 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground, with variation between ground pins limited to 50 mV. |
| 48 | VDD | power_in | Digital supply with a standard operating voltage of 1.71 V to 3.6 V; variation between VDD pins of the same domain is limited to 50 mV. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32L451CCU6TR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32l451ccu6tr-etched.step/stm32l451ccu6tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l451ccu6tr.step/stm32l451ccu6tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (207 pp, sha256
aa4890e697f5f52e, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).