component

STM32L443VCT6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32l443vct6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers stm32l443vct6: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/stm32l443vct6 · Ray 1d ago
stm32l443vct6-etched.glb stm32l443vct6: factory component page (tier=lcsc) · Ray 1d ago
stm32l443vct6-etched.step stm32l443vct6: factory component page (tier=lcsc) · Ray 1d ago
stm32l443vct6-hero.glb stm32l443vct6: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
stm32l443vct6-hero.overlay.json Publish 0.1.0 · Ray 1d ago
stm32l443vct6.glb Publish 0.1.0 · Ray 1d ago
stm32l443vct6.kicad_mod Publish 0.1.0 · Ray 1d ago
stm32l443vct6.kicad_sym Publish 0.1.0 · Ray 1d ago
stm32l443vct6.lbr Publish 0.1.0 · Ray 1d ago
stm32l443vct6.step Publish 0.1.0 · Ray 1d ago

STM32L443VCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32L443VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD); alternate functions TRACECK, TSC_G7_IO1, LCD_SEG38, SAI1_MCLK_A, EVENTOUT.
2 PE3 bidirectional 5 V-tolerant I/O (FT_l, LCD function supplied by VLCD); alternate functions TRACED0, TSC_G7_IO2, LCD_SEG39, SAI1_SD_B, EVENTOUT.
3 PE4 bidirectional 5 V-tolerant I/O (FT); alternate functions TRACED1, TSC_G7_IO3, SAI1_FS_A, EVENTOUT.
4 PE5 bidirectional 5 V-tolerant I/O (FT); alternate functions TRACED2, TSC_G7_IO4, SAI1_SCK_A, EVENTOUT.
5 PE6 bidirectional 5 V-tolerant I/O (FT); alternate functions TRACED3, SAI1_SD_A, EVENTOUT; additional function RTC_TAMP3/WKUP3.
6 VBAT power_in Backup supply for RTC and backup registers; operating range 1.55 V to 3.6 V.
7 PC13 bidirectional I/O (FT) supplied through the power switch, which sinks only 3 mA, so output use is limited to 2 MHz with 30 pF load and no current-source use; alternate function EVENTOUT, additional function RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2.
8 PC14-OSC32_IN bidirectional I/O (FT) supplied through the power switch with the same 3 mA limit as PC13; LSE oscillator input OSC32_IN when the LSE is enabled.
9 PC15-OSC32_OUT bidirectional I/O (FT) supplied through the power switch with the same 3 mA limit as PC13; LSE oscillator output OSC32_OUT when the LSE is enabled.
10 VSS power_in Ground pin; all VDD and VSS pins must be connected to the external supply within the permitted range.
11 VDD power_in Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
12 PH0-OSC_IN bidirectional 5 V-tolerant I/O (FT); alternate function EVENTOUT; OSC_IN high-speed oscillator input (4 to 48 MHz crystal).
13 PH1-OSC_OUT bidirectional 5 V-tolerant I/O (FT); alternate function EVENTOUT; OSC_OUT high-speed oscillator output (4 to 48 MHz crystal).
14 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
15 PC0 bidirectional 5 V-tolerant I/O (FT_fla, analog switch supplied by VDDA, Fm+ capable); alternate functions LPTIM1_IN1, I2C3_SCL, LPUART1_RX, LCD_SEG18, LPTIM2_IN1, EVENTOUT; additional function ADC1_IN1.
16 PC1 bidirectional 5 V-tolerant I/O (FT_fla, analog switch supplied by VDDA, Fm+ capable); alternate functions LPTIM1_OUT, I2C3_SDA, LPUART1_TX, LCD_SEG19, EVENTOUT; additional function ADC1_IN2.
17 PC2 bidirectional 5 V-tolerant I/O (FT_la, analog switch supplied by VDDA); alternate functions LPTIM1_IN2, SPI2_MISO, LCD_SEG20, EVENTOUT; additional function ADC1_IN3.
18 PC3 bidirectional 5 V-tolerant I/O (FT_a, analog switch supplied by VDDA); alternate functions LPTIM1_ETR, SPI2_MOSI, LCD_VLCD, SAI1_SD_A, LPTIM2_ETR, EVENTOUT; additional function ADC1_IN4.
19 VSSA power_in Analog ground pin for ADC, DAC, OPAMP, COMP and VREFBUF.
20 VREF- power_in Negative reference voltage for the ADC; must equal VSSA (negative reference voltage listed as VSSA).
21 VREF+ power_in Positive ADC reference voltage; VREF+ must be at least 2 V when VDDA is 2 V or higher, and equals VDDA when VDDA is below 2 V; additional function VREFBUF_OUT.
22 VDDA power_in Analog supply pin; 1.62 V to 3.6 V when ADC or COMP is used, 1.8 V minimum when DAC or OPAMP is used, and 2.4 V minimum when VREFBUF is used.
23 PA0 bidirectional 5 V-tolerant I/O (FT_a, analog switch supplied by VDDA); alternate functions TIM2_CH1, USART2_CTS, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT; additional functions OPAMP1_VINP, COMP1_INM, ADC1_IN5, RTC_TAMP2/WKUP1.
24 PA1 bidirectional 5 V-tolerant I/O (FT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, LCD_SEG0, TIM15_CH1N, EVENTOUT; additional functions OPAMP1_VINM, COMP1_INP, ADC1_IN6.
25 PA2 bidirectional 5 V-tolerant I/O (FT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG1, COMP2_OUT, TIM15_CH1, EVENTOUT; additional functions COMP2_INM, ADC1_IN7, WKUP4/LSCO.
26 PA3 bidirectional 3.6 V-tolerant I/O (TT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, LCD_SEG2, SAI1_MCLK_A, TIM15_CH2, EVENTOUT; additional functions OPAMP1_VOUT, COMP2_INP, ADC1_IN8.
27 VSS power_in Ground pin; all VDD and VSS pins must be connected to the external supply within the permitted range.
28 VDD power_in Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
29 PA4 bidirectional 3.6 V-tolerant I/O (TT_a, analog switch supplied by VDDA); alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT; additional functions COMP1_INM, COMP2_INM, ADC1_IN9, DAC1_OUT1; injected current limited to -5/0 mA.
30 PA5 bidirectional 3.6 V-tolerant I/O (TT_a, analog switch supplied by VDDA); alternate functions TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, EVENTOUT; additional functions COMP1_INM, COMP2_INM, ADC1_IN10, DAC1_OUT2; injected current limited to -5/0 mA.
31 PA6 bidirectional 5 V-tolerant I/O (FT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions TIM1_BKIN, SPI1_MISO, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, LCD_SEG3, COMP1_OUT/TIM1_BKIN_COMP2, TIM16_CH1, EVENTOUT; additional function ADC1_IN11.
32 PA7 bidirectional 5 V-tolerant I/O (FT_fla, Fm+ capable, analog switch supplied by VDDA); alternate functions TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, COMP2_OUT, EVENTOUT; additional function ADC1_IN12.
33 PC4 bidirectional 5 V-tolerant I/O (FT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions USART3_TX, LCD_SEG22, EVENTOUT; additional functions COMP1_INM, ADC1_IN13.
34 PC5 bidirectional 5 V-tolerant I/O (FT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions USART3_RX, LCD_SEG23, EVENTOUT; additional functions COMP1_INP, ADC1_IN14, WKUP5.
35 PB0 bidirectional 5 V-tolerant I/O (FT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions TIM1_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, LCD_SEG5, COMP1_OUT, SAI1_EXTCLK, EVENTOUT; additional function ADC1_IN15.
36 PB1 bidirectional 5 V-tolerant I/O (FT_la, LCD and analog switch supplied by VLCD/VDDA); alternate functions TIM1_CH3N, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1, EVENTOUT; additional functions COMP1_INM, ADC1_IN16.
37 PB2 bidirectional 5 V-tolerant I/O (FT_a, analog switch supplied by VDDA); alternate functions RTC_OUT, LPTIM1_OUT, I2C3_SMBA, LCD_VLCD, EVENTOUT; additional function COMP1_INP.
38 PE7 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_ETR, SAI1_SD_B, EVENTOUT.
39 PE8 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH1N, SAI1_SCK_B, EVENTOUT.
40 PE9 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH1, SAI1_FS_B, EVENTOUT.
41 PE10 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH2N, TSC_G5_IO1, QUADSPI_CLK, SAI1_MCLK_B, EVENTOUT.
42 PE11 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH2, TSC_G5_IO2, QUADSPI_BK1_NCS, EVENTOUT.
43 PE12 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH3N, SPI1_NSS, TSC_G5_IO3, QUADSPI_BK1_IO0, EVENTOUT.
44 PE13 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH3, SPI1_SCK, TSC_G5_IO4, QUADSPI_BK1_IO1, EVENTOUT.
45 PE14 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, EVENTOUT.
46 PE15 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, EVENTOUT.
47 PB10 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions TIM2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A, EVENTOUT.
48 PB11 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions TIM2_CH4, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG11, COMP2_OUT, EVENTOUT.
49 VSS power_in Ground pin; all VDD and VSS pins must be connected to the external supply within the permitted range.
50 VDD power_in Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
51 PB12 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, LCD_SEG12, SWPMI1_IO, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
52 PB13 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, LCD_SEG13, SWPMI1_TX, SAI1_SCK_A, TIM15_CH1N, EVENTOUT.
53 PB14 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions TIM1_CH2N, I2C2_SDA, SPI2_MISO, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI1_MCLK_A, TIM15_CH1, EVENTOUT.
54 PB15 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions RTC_REFIN, TIM1_CH3N, SPI2_MOSI, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI1_SD_A, TIM15_CH2, EVENTOUT.
55 PD8 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions USART3_TX, LCD_SEG28, EVENTOUT.
56 PD9 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions USART3_RX, LCD_SEG29, EVENTOUT.
57 PD10 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions USART3_CK, TSC_G6_IO1, LCD_SEG30, EVENTOUT.
58 PD11 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions USART3_CTS, TSC_G6_IO2, LCD_SEG31, LPTIM2_ETR, EVENTOUT.
59 PD12 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions USART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, LPTIM2_IN1, EVENTOUT.
60 PD13 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions TSC_G6_IO4, LCD_SEG33, LPTIM2_OUT, EVENTOUT.
61 PD14 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions LCD_SEG34, EVENTOUT.
62 PD15 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions LCD_SEG35, EVENTOUT.
63 PC6 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions TSC_G4_IO1, LCD_SEG24, SDMMC1_D6, EVENTOUT.
64 PC7 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions TSC_G4_IO2, LCD_SEG25, SDMMC1_D7, EVENTOUT.
65 PC8 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions TSC_G4_IO3, LCD_SEG26, SDMMC1_D0, EVENTOUT.
66 PC9 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions TSC_G4_IO4, USB_NOE, LCD_SEG27, SDMMC1_D1, EVENTOUT.
67 PA8 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions MCO, TIM1_CH1, USART1_CK, LCD_COM0, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT.
68 PA9 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions TIM1_CH2, I2C1_SCL, USART1_TX, LCD_COM1, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
69 PA10 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions TIM1_CH3, I2C1_SDA, USART1_RX, USB_CRS_SYNC, LCD_COM2, SAI1_SD_A, EVENTOUT.
70 PA11 bidirectional 5 V-tolerant I/O (FT_u, USB function supplied by VDDUSB); alternate functions TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, CAN1_RX, USB_DM, TIM1_BKIN2_COMP1, EVENTOUT; additional function COMP1_OUT.
71 PA12 bidirectional 5 V-tolerant I/O (FT_u, USB function supplied by VDDUSB); alternate functions TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, USB_DP, EVENTOUT.
72 PA13 (JTMS-SWDIO) bidirectional 5 V-tolerant I/O (FT); after reset configured as JTMS-SWDIO with internal pull-up enabled; alternate functions IR_OUT, USB_NOE, SWPMI1_TX, SAI1_SD_B, EVENTOUT.
73 VDDUSB power_in USB supply pin; 3.0 V to 3.6 V when USB is used, and 0 to 3.6 V when USB is not used.
74 VSS power_in Ground pin; all VDD and VSS pins must be connected to the external supply within the permitted range.
75 VDD power_in Digital supply pin; standard operating voltage 1.71 V to 3.6 V.
76 PA14 (JTCK-SWCLK) bidirectional 5 V-tolerant I/O (FT); after reset configured as JTCK-SWCLK with internal pull-down enabled; alternate functions LPTIM1_OUT, I2C1_SMBA, SWPMI1_RX, SAI1_FS_B, EVENTOUT.
77 PA15 (JTDI) bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); after reset configured as JTDI with internal pull-up enabled; alternate functions TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, TSC_G3_IO1, LCD_SEG17, SWPMI1_SUSPEND, EVENTOUT.
78 PC10 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions SPI3_SCK, USART3_TX, TSC_G3_IO2, LCD_COM4/LCD_SEG28/LCD_SEG40, SDMMC1_D2, EVENTOUT.
79 PC11 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions SPI3_MISO, USART3_RX, TSC_G3_IO3, LCD_COM5/LCD_SEG29/LCD_SEG41, SDMMC1_D3, EVENTOUT.
80 PC12 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions SPI3_MOSI, USART3_CK, TSC_G3_IO4, LCD_COM6/LCD_SEG30/LCD_SEG42, SDMMC1_CK, EVENTOUT.
81 PD0 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_NSS, CAN1_RX, EVENTOUT.
82 PD1 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_SCK, CAN1_TX, EVENTOUT.
83 PD2 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions USART3_RTS_DE, TSC_SYNC, LCD_COM7/LCD_SEG31/LCD_SEG43, SDMMC1_CMD, EVENTOUT.
84 PD3 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_MISO, USART2_CTS, QUADSPI_BK2_NCS, EVENTOUT.
85 PD4 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_MOSI, USART2_RTS_DE, QUADSPI_BK2_IO0, EVENTOUT.
86 PD5 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_TX, QUADSPI_BK2_IO1, EVENTOUT.
87 PD6 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_RX, QUADSPI_BK2_IO2, SAI1_SD_A, EVENTOUT.
88 PD7 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_CK, QUADSPI_BK2_IO3, EVENTOUT.
89 PB3 (JTDO-TRACESWO) bidirectional 5 V-tolerant I/O (FT_la, analog switch supplied by VDDA); after reset configured as JTDO-TRACESWO; alternate functions TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, LCD_SEG7, SAI1_SCK_B, EVENTOUT; additional function COMP2_INM.
90 PB4 (NJTRST) bidirectional 5 V-tolerant I/O (FT_fla, analog switch supplied by VDDA); after reset configured as NJTRST with internal pull-up enabled; alternate functions I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, TSC_G2_IO1, LCD_SEG8, SAI1_MCLK_B, EVENTOUT; additional function COMP2_INP.
91 PB5 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, TSC_G2_IO2, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT.
92 PB6 bidirectional 5 V-tolerant I/O (FT_fa, Fm+ capable, analog switch supplied by VDDA); alternate functions LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N, EVENTOUT; additional function COMP2_INP.
93 PB7 bidirectional 5 V-tolerant I/O (FT_fla, Fm+ capable, analog switch supplied by VDDA); alternate functions LPTIM1_IN2, I2C1_SDA, USART1_RX, TSC_G2_IO4, LCD_SEG21, EVENTOUT; additional functions COMP2_INM, PVD_IN.
94 PH3-BOOT0 bidirectional 5 V-tolerant I/O (FT) that also serves as the BOOT0 boot-mode pin; alternate function EVENTOUT.
95 PB8 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions I2C1_SCL, CAN1_RX, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT.
96 PB9 bidirectional 5 V-tolerant I/O (FT_fl, Fm+ capable, LCD supplied by VLCD); alternate functions IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, LCD_COM3, SDMMC1_D5, SAI1_FS_A, EVENTOUT.
97 PE0 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions LCD_SEG36, TIM16_CH1, EVENTOUT.
98 PE1 bidirectional 5 V-tolerant I/O (FT_l, LCD supplied by VLCD); alternate functions LCD_SEG37, EVENTOUT.
99 VSS power_in Ground pin; all VDD and VSS pins must be connected to the external supply within the permitted range.
100 VDD power_in Digital supply pin; standard operating voltage 1.71 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32L443VCT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32l443vct6-etched.step / stm32l443vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l443vct6.step / stm32l443vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (220 pp, sha256 20193b27a61dfbca, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF