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STM32L431RBT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32L431RBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32L431RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply for the RTC and 32x32-bit backup registers, with a backup operating voltage of 1.55 V to 3.6 V.
2 PC13 bidirectional FT I/O supplied through the power switch, so output speed must not exceed 2 MHz with a 30 pF maximum load and it must not be used as a current source (note 1); also RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2, EVENTOUT.
3 PC14-OSC32_IN (PC14) bidirectional FT I/O with the same power-switch limits as PC13 (2 MHz, 30 pF, no current-source use); alternate function OSC32_IN (low-speed oscillator input).
4 PC15-OSC32_OUT (PC15) bidirectional FT I/O with the same power-switch limits as PC13 (2 MHz, 30 pF, no current-source use); alternate function OSC32_OUT (low-speed oscillator output).
5 PH0-OSC_IN (PH0) bidirectional FT I/O; additional function OSC_IN (oscillator input), with EVENTOUT as alternate function.
6 PH1-OSC_OUT (PH1) bidirectional FT I/O; additional function OSC_OUT (oscillator output), with EVENTOUT as alternate function.
7 NRST bidirectional Bidirectional reset pin with an embedded weak pull-up resistor (RST structure).
8 PC0 bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) with ADC1_IN1; alternates LPTIM1_IN1, I2C3_SCL, LPUART1_RX, LPTIM2_IN1, EVENTOUT.
9 PC1 bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) with ADC1_IN2; alternates LPTIM1_OUT, I2C3_SDA, LPUART1_TX, EVENTOUT.
10 PC2 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with ADC1_IN3; alternates LPTIM1_IN2, SPI2_MISO, EVENTOUT.
11 PC3 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with ADC1_IN4; alternates LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR, EVENTOUT.
12 VSSA/VREF- power_in Analog ground and negative ADC reference voltage; VREF- can be internally connected to VSSA depending on the package.
13 VDDA/VREF+ power_in Analog supply (1.62 V to 3.6 V when ADC or COMP is used) and positive ADC reference VREF+, which can be internally connected to VDDA depending on the package.
14 PA0 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with ADC1_IN5, OPAMP1_VINP, COMP1_INM, RTC_TAMP2, WKUP1; alternates TIM2_CH1, USART2_CTS, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT.
15 PA1 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with ADC1_IN6, OPAMP1_VINM, COMP1_INP; alternates TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, TIM15_CH1N, EVENTOUT.
16 PA2 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with ADC1_IN7, COMP2_INM, WKUP4, LSCO; alternates TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, TIM15_CH1, EVENTOUT.
17 PA3 bidirectional TT_a I/O (3.6 V tolerant, analog switch supplied by VDDA) with OPAMP1_VOUT, COMP2_INP, ADC1_IN8; alternates TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, SAI1_MCLK_A, TIM15_CH2, EVENTOUT.
18 VSS power_in Ground reference.
19 VDD power_in Standard operating supply voltage, 1.71 V to 3.6 V.
20 PA4 bidirectional TT_a I/O (3.6 V tolerant, analog switch supplied by VDDA) with COMP1_INM, COMP2_INM, ADC1_IN9, DAC1_OUT1; alternates SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT.
21 PA5 bidirectional TT_a I/O (3.6 V tolerant, analog switch supplied by VDDA) with COMP1_INM, COMP2_INM, ADC1_IN10, DAC1_OUT2; alternates TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, EVENTOUT.
22 PA6 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with ADC1_IN11; alternates TIM1_BKIN, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, TIM1_BKIN_COMP2, TIM16_CH1, EVENTOUT.
23 PA7 bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) with ADC1_IN12; alternates TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, COMP2_OUT, EVENTOUT.
24 PC4 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with COMP1_INM, ADC1_IN13; alternates USART3_TX, EVENTOUT.
25 PC5 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with COMP1_INP, ADC1_IN14, WKUP5; alternates USART3_RX, EVENTOUT.
26 PB0 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with ADC1_IN15; alternates TIM1_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT, SAI1_EXTCLK, EVENTOUT.
27 PB1 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with COMP1_INM, ADC1_IN16; alternates TIM1_CH3N, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1, EVENTOUT.
28 PB2 bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) with COMP1_INP; alternates RTC_OUT, LPTIM1_OUT, I2C3_SMBA, EVENTOUT.
29 PB10 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates TIM2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, COMP1_OUT, SAI1_SCK_A, EVENTOUT.
30 PB11 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates TIM2_CH4, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, EVENTOUT.
31 VSS power_in Ground reference.
32 VDD power_in Standard operating supply voltage, 1.71 V to 3.6 V.
33 PB12 bidirectional FT I/O (5 V tolerant); alternates TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, SWPMI1_IO, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
34 PB13 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SWPMI1_TX, SAI1_SCK_A, TIM15_CH1N, EVENTOUT.
35 PB14 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates TIM1_CH2N, I2C2_SDA, SPI2_MISO, USART3_RTS_DE, TSC_G1_IO3, SWPMI1_RX, SAI1_MCLK_A, TIM15_CH1, EVENTOUT.
36 PB15 bidirectional FT I/O (5 V tolerant); alternates RTC_REFIN, TIM1_CH3N, SPI2_MOSI, TSC_G1_IO4, SWPMI1_SUSPEND, SAI1_SD_A, TIM15_CH2, EVENTOUT.
37 PC6 bidirectional FT I/O (5 V tolerant); alternates TSC_G4_IO1, SDMMC1_D6, EVENTOUT.
38 PC7 bidirectional FT I/O (5 V tolerant); alternates TSC_G4_IO2, SDMMC1_D7, EVENTOUT.
39 PC8 bidirectional FT I/O (5 V tolerant); alternates TSC_G4_IO3, SDMMC1_D0, EVENTOUT.
40 PC9 bidirectional FT I/O (5 V tolerant); alternates TSC_G4_IO4, SDMMC1_D1, EVENTOUT.
41 PA8 bidirectional FT I/O (5 V tolerant); alternates MCO, TIM1_CH1, USART1_CK, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT.
42 PA9 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates TIM1_CH2, I2C1_SCL, USART1_TX, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
43 PA10 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates TIM1_CH3, I2C1_SDA, USART1_RX, SAI1_SD_A, EVENTOUT.
44 PA11 bidirectional FT_u I/O; alternates TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1, EVENTOUT.
45 PA12 bidirectional FT_u I/O; alternates TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, EVENTOUT.
46 PA13 (JTMS-SWDIO) bidirectional FT I/O that is configured as the JTMS-SWDIO debug function after reset with its internal pull-up activated (note 3); also IR_OUT, SWPMI1_TX, SAI1_SD_B, EVENTOUT.
47 VSS power_in Ground reference.
48 VDD power_in Standard operating supply voltage, 1.71 V to 3.6 V.
49 PA14 (JTCK-SWCLK) bidirectional FT I/O that is configured as the JTCK-SWCLK debug function after reset with its internal pull-down activated (note 3); also LPTIM1_OUT, I2C1_SMBA, SWPMI1_RX, SAI1_FS_B, EVENTOUT.
50 PA15 (JTDI) bidirectional FT I/O that is configured as the JTDI debug function after reset with its internal pull-up activated (note 3); also TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, TSC_G3_IO1, SWPMI1_SUSPEND, EVENTOUT.
51 PC10 bidirectional FT I/O (5 V tolerant); alternates SPI3_SCK, USART3_TX, TSC_G3_IO2, SDMMC1_D2, EVENTOUT.
52 PC11 bidirectional FT I/O (5 V tolerant); alternates SPI3_MISO, USART3_RX, TSC_G3_IO3, SDMMC1_D3, EVENTOUT.
53 PC12 bidirectional FT I/O (5 V tolerant); alternates SPI3_MOSI, USART3_CK, TSC_G3_IO4, SDMMC1_CK, EVENTOUT.
54 PD2 bidirectional FT I/O (5 V tolerant); alternates USART3_RTS_DE, TSC_SYNC, SDMMC1_CMD, EVENTOUT.
55 PB3 (JTDO-TRACESWO) bidirectional FT_a I/O (5 V tolerant, analog switch supplied by VDDA) configured as the JTDO-TRACESWO debug function after reset (note 3); also COMP2_INM, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B, EVENTOUT.
56 PB4 (NJTRST) bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) configured as NJTRST with its internal pull-up activated after reset (note 3); also COMP2_INP, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, TSC_G2_IO1, SAI1_MCLK_B, EVENTOUT.
57 PB5 bidirectional FT I/O (5 V tolerant); alternates LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT.
58 PB6 bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) with COMP2_INP; alternates LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N, EVENTOUT.
59 PB7 bidirectional FT_fa I/O (5 V tolerant, Fm+ capable, analog switch supplied by VDDA) with COMP2_INM and PVD_IN; alternates LPTIM1_IN2, I2C1_SDA, USART1_RX, TSC_G2_IO4, EVENTOUT.
60 PH3/BOOT0 bidirectional FT I/O (5 V tolerant) whose additional function is BOOT0, the boot mode selection pin; also EVENTOUT.
61 PB8 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates I2C1_SCL, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT.
62 PB9 bidirectional FT_f I/O (5 V tolerant, Fm+ capable); alternates IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, SDMMC1_D5, SAI1_FS_A, EVENTOUT.
63 VSS power_in Ground reference.
64 VDD power_in Standard operating supply voltage, 1.71 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32L431RBT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32l431rbt6-etched.step / stm32l431rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l431rbt6.step / stm32l431rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (200 pp, sha256 fc652d7acd05c2a9, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF