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STM32L152V8T6A

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32l152v8t6afactory-2.0.0extractor-text
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Symbol & Footprint

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Contents

README

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STM32L152V8T6A

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32L152V8T6A from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO port E pin 2, 5V tolerant I/O capable of trace clock, LCD segment 38, or timer 3 external trigger.
2 PE3 bidirectional GPIO port E pin 3, 5V tolerant I/O capable of trace data 0, LCD segment 39, or timer 3 channel 1.
3 PE4 bidirectional GPIO port E pin 4, 5V tolerant I/O capable of trace data 1 or timer 3 channel 2.
4 PE5 bidirectional GPIO port E pin 5, 5V tolerant I/O capable of trace data 2 or timer 9 channel 1.
5 PE6-WKUP3 bidirectional GPIO port E pin 6 with wakeup capability 3, 5V tolerant I/O capable of trace data 3, timer 9 channel 2, RTC tamper 3 input.
6 VLCD power_in LCD positive supply pin for LCD driver step-up converter output, applicable to STM32L152 devices only.
7 PC13-WKUP2 bidirectional GPIO port C pin 13 with wakeup capability 2, 5V tolerant I/O capable of RTC tamper 1, RTC timestamp, or RTC output.
8 PC14-OSC32_IN bidirectional GPIO port C pin 14 or low-speed external oscillator input, standard 3.3V I/O, priority given to LSE oscillator when enabled.
9 PC15-OSC32_OUT bidirectional GPIO port C pin 15 or low-speed external oscillator output, standard 3.3V I/O, priority given to LSE oscillator when enabled.
10 VSS_5 power_in Ground supply pin, reference potential 0 V.
11 VDD_5 power_in Positive power supply pin for core and I/O, voltage range 1.65 V to 3.6 V.
12 PH0-OSC_IN bidirectional GPIO port H pin 0 or high-speed external oscillator input, standard 3.3V I/O, priority given to HSE oscillator when enabled.
13 PH1-OSC_OUT bidirectional GPIO port H pin 1 or high-speed external oscillator output, standard 3.3V I/O, priority given to HSE oscillator when enabled.
14 NRST bidirectional Reset input pin with embedded weak pull-up resistor, active low reset signal, bidirectional capability.
15 PC0 bidirectional GPIO port C pin 0, 5V tolerant I/O capable of LCD segment 18 or ADC input 10 with comparator 1 input.
16 PC1 bidirectional GPIO port C pin 1, 5V tolerant I/O capable of LCD segment 19 or ADC input 11 with comparator 1 input.
17 PC2 bidirectional GPIO port C pin 2, 5V tolerant I/O capable of LCD segment 20 or ADC input 12 with comparator 1 input.
18 PC3 bidirectional GPIO port C pin 3, standard 3.3V I/O capable of LCD segment 21 or ADC input 13 with comparator 1 input.
19 VSSA power_in Analog ground supply pin, voltage reference 0 V.
20 VREF- power_in ADC negative reference voltage pin, voltage range 0 V to VDDA, must be tied to ground or VSSA.
21 VREF+ power_in ADC positive reference voltage pin, voltage range 1.8 V to VDDA, can be grounded if ADC and DAC not used.
22 VDDA power_in Analog positive supply pin for ADC, DAC, and analog peripherals, voltage range 1.8 V to 3.6 V.
23 PA0-WKUP1 bidirectional GPIO port A pin 0 with wakeup capability 1, 5V tolerant I/O capable of USART2 clear-to-send or timer 2 channel 1 external trigger with ADC and RTC functions.
24 PA1 bidirectional GPIO port A pin 1, 5V tolerant I/O capable of USART2 request-to-send, timer 2 channel 2, or LCD segment 0 with ADC input 1.
25 PA2 bidirectional GPIO port A pin 2, 5V tolerant I/O capable of USART2 transmit, timer 2 channel 3, timer 9 channel 1, or LCD segment 1 with ADC input 2.
26 PA3 bidirectional GPIO port A pin 3, standard 3.3V I/O capable of USART2 receive, timer 2 channel 4, timer 9 channel 2, or LCD segment 2 with ADC input 3.
27 VSS_4 power_in Ground supply pin, reference potential 0 V.
28 VDD_4 power_in Positive power supply pin for core and I/O, voltage range 1.65 V to 3.6 V.
29 PA4 bidirectional GPIO port A pin 4, standard 3.3V I/O capable of SPI1 chip select, USART2 clock, DAC output 1, or ADC input 4 with comparator 1 input.
30 PA5 bidirectional GPIO port A pin 5, standard 3.3V I/O capable of SPI1 clock, timer 2 channel 1 external trigger, DAC output 2, or ADC input 5 with comparator 1 input.
31 PA6 bidirectional GPIO port A pin 6, 5V tolerant I/O capable of SPI1 master-in-slave-out, timer 3 channel 1, timer 10 channel 1, or LCD segment 3 with ADC input 6.
32 PA7 bidirectional GPIO port A pin 7, 5V tolerant I/O capable of SPI1 master-out-slave-in, timer 3 channel 2, timer 11 channel 1, or LCD segment 4 with ADC input 7.
33 PC4 bidirectional GPIO port C pin 4, 5V tolerant I/O capable of LCD segment 22 or ADC input 14 with comparator 1 input.
34 PC5 bidirectional GPIO port C pin 5, 5V tolerant I/O capable of LCD segment 23 or ADC input 15 with comparator 1 input.
35 PB0 bidirectional GPIO port B pin 0, standard 3.3V I/O capable of timer 3 channel 3, LCD segment 5, ADC input 8, or VLCD rail 3 output.
36 PB1 bidirectional GPIO port B pin 1, 5V tolerant I/O capable of timer 3 channel 4, LCD segment 6, ADC input 9, or voltage reference output.
37 PB2/BOOT1 bidirectional GPIO port B pin 2 with BOOT1 function, 5V tolerant I/O capable of VLCD rail 1 output, boot mode selection.
38 PE7 bidirectional GPIO port E pin 7, standard 3.3V I/O capable of ADC input 22 with comparator 1 input.
39 PE8 bidirectional GPIO port E pin 8, standard 3.3V I/O capable of ADC input 23 with comparator 1 input.
40 PE9 bidirectional GPIO port E pin 9, standard 3.3V I/O capable of timer 2 channel 1 external trigger or ADC input 24 with comparator 1 input.
41 PE10 bidirectional GPIO port E pin 10, standard 3.3V I/O capable of timer 2 channel 2 or ADC input 25 with comparator 1 input.
42 PE11 bidirectional GPIO port E pin 11, 5V tolerant I/O capable of timer 2 channel 3 or VLCD rail 2 output.
43 PE12 bidirectional GPIO port E pin 12, 5V tolerant I/O capable of timer 2 channel 4, SPI1 chip select, or VLCD rail 3 output.
44 PE13 bidirectional GPIO port E pin 13, 5V tolerant I/O capable of SPI1 clock.
45 PE14 bidirectional GPIO port E pin 14, 5V tolerant I/O capable of SPI1 master-in-slave-out.
46 PE15 bidirectional GPIO port E pin 15, 5V tolerant I/O capable of SPI1 master-out-slave-in.
47 PB10 bidirectional GPIO port B pin 10, 5V tolerant I/O capable of I2C2 clock, USART3 transmit, timer 2 channel 3, or LCD segment 10.
48 PB11 bidirectional GPIO port B pin 11, 5V tolerant I/O capable of I2C2 data, USART3 receive, timer 2 channel 4, or LCD segment 11.
49 VSS_1 power_in Ground supply pin, reference potential 0 V.
50 VDD_1 power_in Positive power supply pin for core and I/O, voltage range 1.65 V to 3.6 V.
51 PB12 bidirectional GPIO port B pin 12, 5V tolerant I/O capable of SPI2 chip select, I2C2 SMBus alert, USART3 clock, timer 10 channel 1, or LCD segment 12 with ADC and VLCD functions.
52 PB13 bidirectional GPIO port B pin 13, 5V tolerant I/O capable of SPI2 clock, USART3 clear-to-send, timer 9 channel 1, or LCD segment 13 with ADC input 19.
53 PB14 bidirectional GPIO port B pin 14, 5V tolerant I/O capable of SPI2 master-in-slave-out, USART3 request-to-send, timer 9 channel 2, or LCD segment 14 with ADC input 20.
54 PB15 bidirectional GPIO port B pin 15, 5V tolerant I/O capable of SPI2 master-out-slave-in, timer 11 channel 1, or LCD segment 15 with ADC and RTC functions.
55 PD8 bidirectional GPIO port D pin 8, 5V tolerant I/O capable of USART3 transmit or LCD segment 28.
56 PD9 bidirectional GPIO port D pin 9, 5V tolerant I/O capable of USART3 receive or LCD segment 29.
57 PD10 bidirectional GPIO port D pin 10, 5V tolerant I/O capable of USART3 clock or LCD segment 30.
58 PD11 bidirectional GPIO port D pin 11, 5V tolerant I/O capable of USART3 clear-to-send or LCD segment 31.
59 PD12 bidirectional GPIO port D pin 12, 5V tolerant I/O capable of timer 4 channel 1, USART3 request-to-send, or LCD segment 32.
60 PD13 bidirectional GPIO port D pin 13, 5V tolerant I/O capable of timer 4 channel 2 or LCD segment 33.
61 PD14 bidirectional GPIO port D pin 14, 5V tolerant I/O capable of timer 4 channel 3 or LCD segment 34.
62 PD15 bidirectional GPIO port D pin 15, 5V tolerant I/O capable of timer 4 channel 4 or LCD segment 35.
63 PC6 bidirectional GPIO port C pin 6, 5V tolerant I/O capable of timer 3 channel 1 or LCD segment 24.
64 PC7 bidirectional GPIO port C pin 7, 5V tolerant I/O capable of timer 3 channel 2 or LCD segment 25.
65 PC8 bidirectional GPIO port C pin 8, 5V tolerant I/O capable of timer 3 channel 3 or LCD segment 26.
66 PC9 bidirectional GPIO port C pin 9, 5V tolerant I/O capable of timer 3 channel 4 or LCD segment 27.
67 PA8 bidirectional GPIO port A pin 8, 5V tolerant I/O capable of USART1 clock, microcontroller clock output, or LCD common 0 output.
68 PA9 bidirectional GPIO port A pin 9, 5V tolerant I/O capable of USART1 transmit or LCD common 1 output.
69 PA10 bidirectional GPIO port A pin 10, 5V tolerant I/O capable of USART1 receive or LCD common 2 output.
70 PA11 bidirectional GPIO port A pin 11, 5V tolerant I/O capable of USART1 clear-to-send, SPI1 master-in-slave-out, or USB data minus signal.
71 PA12 bidirectional GPIO port A pin 12, 5V tolerant I/O capable of USART1 request-to-send, SPI1 master-out-slave-in, or USB data plus signal.
72 PA13 bidirectional GPIO port A pin 13, 5V tolerant I/O configured as JTAG test mode select or serial wire debug data I/O.
73 PH2 bidirectional GPIO port H pin 2, 5V tolerant I/O.
74 VSS_2 power_in Ground supply pin, reference potential 0 V.
75 VDD_2 power_in Positive power supply pin for core and I/O, voltage range 1.65 V to 3.6 V.
76 PA14 bidirectional GPIO port A pin 14, 5V tolerant I/O configured as JTAG clock or serial wire debug clock.
77 PA15 bidirectional GPIO port A pin 15, 5V tolerant I/O configured as JTAG data input or capable of timer 2 channel 1 external trigger, SPI1 chip select, and LCD segment 17.
78 PC10 bidirectional GPIO port C pin 10, 5V tolerant I/O capable of USART3 transmit or LCD common 4 output with segment functions.
79 PC11 bidirectional GPIO port C pin 11, 5V tolerant I/O capable of USART3 receive or LCD common 5 output with segment functions.
80 PC12 bidirectional GPIO port C pin 12, 5V tolerant I/O capable of USART3 clock or LCD common 6 output with segment functions.
81 PD0 bidirectional GPIO port D pin 0, 5V tolerant I/O capable of SPI2 chip select or timer 9 channel 1.
82 PD1 bidirectional GPIO port D pin 1, 5V tolerant I/O capable of SPI2 clock.
83 PD2 bidirectional GPIO port D pin 2, 5V tolerant I/O capable of timer 3 external trigger or LCD common 7 output with segment functions.
84 PD3 bidirectional GPIO port D pin 3, 5V tolerant I/O capable of USART2 clear-to-send or SPI2 master-in-slave-out.
85 PD4 bidirectional GPIO port D pin 4, 5V tolerant I/O capable of USART2 request-to-send or SPI2 master-out-slave-in.
86 PD5 bidirectional GPIO port D pin 5, 5V tolerant I/O capable of USART2 transmit.
87 PD6 bidirectional GPIO port D pin 6, 5V tolerant I/O capable of USART2 receive.
88 PD7 bidirectional GPIO port D pin 7, 5V tolerant I/O capable of USART2 clock or timer 9 channel 2.
89 PB3 bidirectional GPIO port B pin 3, 5V tolerant I/O configured as JTAG data output or capable of timer 2 channel 2, SPI1 clock, LCD segment 7 with comparator 2 input.
90 PB4 bidirectional GPIO port B pin 4, 5V tolerant I/O configured as JTAG non-trst or capable of timer 3 channel 1, SPI1 master-in-slave-out, LCD segment 8 with comparator 2 input.
91 PB5 bidirectional GPIO port B pin 5, 5V tolerant I/O capable of I2C1 SMBus alert, timer 3 channel 2, SPI1 master-out-slave-in, or LCD segment 9 with comparator 2 input.
92 PB6 bidirectional GPIO port B pin 6, 5V tolerant I/O capable of I2C1 clock, timer 4 channel 1, or USART1 transmit.
93 PB7 bidirectional GPIO port B pin 7, 5V tolerant I/O capable of I2C1 data, timer 4 channel 2, or USART1 receive with programmable voltage detector input.
94 BOOT0 input Boot mode selection pin, logic level determines whether device boots from main flash memory or embedded bootloader.
95 PB8 bidirectional GPIO port B pin 8, 5V tolerant I/O capable of timer 4 channel 3, I2C1 clock, timer 10 channel 1, or LCD segment 16.
96 PB9 bidirectional GPIO port B pin 9, 5V tolerant I/O capable of timer 4 channel 4, I2C1 data, timer 11 channel 1, or LCD common 3 output.
97 PE0 bidirectional GPIO port E pin 0, 5V tolerant I/O capable of timer 4 external trigger, timer 10 channel 1, or LCD segment 36.
98 PE1 bidirectional GPIO port E pin 1, 5V tolerant I/O capable of timer 11 channel 1 or LCD segment 37.
99 VSS_3 power_in Ground supply pin, reference potential 0 V.
100 VDD_3 power_in Positive power supply pin for core and I/O, voltage range 1.65 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32L152V8T6A
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32l152v8t6a-etched.step / stm32l152v8t6a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l152v8t6a.step / stm32l152v8t6a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (130 pp, sha256 e5e0ab791f4e7879, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF